NS32829

· Makes DRAM interface and refresh tasks appear virtually transparent to the CPU making DRAMs as easy to use as static RAMs
· Specifically designed to eliminate CPU wait states up to 10 MHz or beyond
· Eliminates 20 discrete components for significant board real estate reduction, system power savings and the elimination of chip-to-chip AC skewing
· On-board ultra precise delay line
· On-board high capacitive RAS, CAS, WE and Address drivers (specified driving 88 DRAMs directly)
· AC specified for directly addressing up to 8 Mbytes
· Low power/high speed bipolar oxide isolated process
· Downward pin and function compatible with 256k DRAM Controller/Drivers DP8409A, DP8417, DP8418, and DP8419

· Automatic access to memory (in mode 5 only one signal, RASIN, is required in order to access memory)
· Hidden refresh capability (refreshes are performed automatically while in mode 5 when non-local accesses are taking place, as determined by CS)
· Refresh request capability (if no hidden refresh took place while RFCK was high, a refresh request is generated at the RFI/O pin when RFCK goes high)
· Automatic forced refresh (If a refresh request is generated while in mode 5, as described above, external logic should switch the DP8429 into mode 1 to do an automatic forced refresh. No other external control signals need be issued. WAIT states can be inserted into the processor machine cycles if the system tries to access memory while the DP8429 is in mode 1 doing a forced refresh).

The DP8428 and DP8429 1M DRAM Controller/Drivers are designed to provide ``No-Waitstate'' CPU interface to Dynamic RAM arrays of up to 8 Mbytes and larger. The DP8428 and DP8429 are tailored for 32-bit and 16-bit system requirements, respectively. Both devices are fabricated using National's new oxide isolated Advanced Low power Schottky (ALS) process and use design techniques which enable them to significantly out-perform all other LSI or discrete alternatives in speed, level of integration, and power consumption.

Each device DP8428 and DP8429 integrates the following critical 1M DRAM controller functions on a single monolithic device: ultra precise delay line; 9 bit refresh counter; fall-through row, column, and bank select input latches; Row/Column address muxing logic; on-board high capacitive-load RAS, CAS, Write Enable and Address output drivers; and, precise control signal timing for all the above.

In order to specify each device DP8428 and DP8429 for ``true'' worst case operating conditions, all timing parameters are guaranteed while the chip is driving the capacitive load of 88 DRAMs including trace capacitance. The chip's delay timing logic makes use of a patented new delay line technique which keeps AC skew to g3 ns over the full VCC range of g10% and temperature range of b55ßC to a125ßC. The DP8428 and DP8429 guarantee a maximum RASIN to CASOUT delay of 80 ns or 70 ns even while driving an 8 Mbyte memory array with error correction check bits included. Two speed selected options of these devices are shown in the switching characteristics section of this document.