Features: • Maximum Input Clock Frequency 6 GHz Typical• Maximum Input Data Rate 6 Gb/s Typical• Low 14 mA Typical Power Supply Current• 150 ps Typical Propagation Delay• 5 ps Typical Within Device Skew• 75 ps Typical Rise/Fall Times• PECL Mode Operating...
NB6L11: Features: • Maximum Input Clock Frequency 6 GHz Typical• Maximum Input Data Rate 6 Gb/s Typical• Low 14 mA Typical Power Supply Current• 150 ps Typical Propagation Delay...
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Symbol |
Parameter |
Condition 1 |
Condition 2 |
Rating |
Units |
VCC |
Positive Power Supply | VEE = 0 V |
3.6 |
V | |
VEE |
Negative Power Supply | VCC = 0 V |
-3.6 |
V | |
VI |
Positive Input Voltage Negative Input Voltage |
VEE = 0 V VCC = 0 V |
VI VCC VI VEE |
3.6 -3.6 |
V V |
VINPP |
Differential Input Voltage |D − D| | VCC − VEE 2.8 V VCC − VEE < 2.8 V |
2.8 |VCC − VEE| |
V | |
Iout |
Output Current | Continuous Surge |
25 50 |
mA mA | |
TA |
Operating Temperature Range |
−40 to +85 |
|||
Tstg |
Storage Temperature Range |
−65 to +150 |
|||
JA |
Thermal Resistance (Junction−to−Ambient) | 0 lfpm 500 lfpm |
SOIC−8 SOIC−8 |
190 130 |
/W /W |
JC |
Thermal Resistance (Junction−to−Case) | Standard Board |
SOIC−8 |
41 to 44 |
/W |
JA |
Thermal Resistance (Junction−to−Ambient) | 0 lfpm 500 lfpm |
TSSOP−8 |
185 140 |
/W /W |
JC |
Thermal Resistance (Junction−to−Case) | Standard Board |
TSSOP−8 |
41 to 44 |
/W |
Tsol |
Wave Solder | < 3 sec @ 248°C |
265 |
Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device unctional operation is not implied, damage may occur and reliability may be affected.
The NB6L11 is an enhanced differential 1:2 clock or data fanout buffer/translator. The NB6L11 has the same pinout and is functionally equivalent to the LVEL11, EP11, LVEP11 devices. Moreover, the device is optimized for the systems that require LOW skew, LOW jitter and LOW power consumption.Differential input can be configured to accept single−ended signal by applying an external reference voltage to unused complimentary input pin. Input accept LVNECL, LVPECL, LVTTL, LVCMOS, CML, or LVDS. The outputs are 800 mV ECL signals.