Features: · Timing From Microseconds to Hours
· Adjustable Duty Cycle
· Astable or Monostable Operation
· TTL-Compatible Output Can Sink or Source up to 200 mASpecifications
|
MIN MAX |
UNIT |
| VCC Supply voltage(2) |
18 |
V |
| VI Input voltage |
CONT, RESET, THRES, TRIG |
VCC |
V |
| IO Output current |
±225 |
mA |
| qJA Package thermal impedance(3) (4) |
D package |
97 |
/W |
| P package |
85 |
| PS package |
95 |
| PW package |
149 |
| qJC Package thermal impedance(5) (6) |
FK package |
5.61 |
/W |
| JG package |
14.5 |
| TJ Operating virtual junction temperature |
150 |
|
| Case temperature for 60 s |
FK package |
260 |
|
| Lead temperature 1, 6 mm (1/16 in) from case for 60 s |
JG package |
300 |
|
| Tstg Storage temperature range |
65 150 |
|
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating onditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to GND.
(3) Maximum power dissipation is a function of TJ(max), qJA, and TA. The maximum allowable power dissipation at any allowable ambient temperature is PD = (TJ(max) - TA)/qJA. Operating at the absolute maximum TJ of 150°C can affect reliability.
(4) The package thermal impedance is calculated in accordance with JESD 51-7.
(5) Maximum power dissipation is a function of TJ(max), qJC, and TC. The maximum allowable power dissipation at any allowable case
temperature is PD = (TJ(max) - TC)/qJC. Operating at the absolute maximum TJ of 150°C can affect reliability.
(6) The package thermal impedance is calculated in accordance with MIL-STD-883.
DescriptionThese NA555 devices are precision timing circuits capable of producing accurate time delays or oscillation. In the time-delay or monostable mode of operation, the timed interval is controlled by a single external resistor and capacitor network. In the astable mode of operation, the frequency and duty cycle can be controlled independently with two external resistors and a single external capacitor.
The threshold and trigger levels of NA555 normally are two-thirds and one-third, respectively, of VCC. These levels can be altered by use of the control-voltage terminal. When the trigger input falls below the trigger level, the flip-flop is set, and the output goes high. If the trigger input is above the trigger level and the threshold input is above the threshold level, the flip-flop is reset and the output is low. The reset (RESET) input can override all other inputs and can be used to initiate a new timing cycle. When RESET goes low, the flip-flop is reset, and the output goes low. When the output is low, a low-impedance path is provided between discharge (DISCH) and ground.
The NA555 output circuit is capable of sinking or sourcing current up to 200 mA. Operation is specified for supplies of 5 V to 15 V. With a 5-V supply, output levels are compatible with TTL inputs.
NA555 Data Sheet
