N80C186-25

The N80C186-25 is a CMOS high-integration microprocessor.It has features that are new to the family,which include a DRAM refresh control unit and power-save mode.When used in control unit,and power-save mode.When used in "compatible" mode,the product is 100% pin-for-pin compatible with the NMOS N80C186-25 (except for 8087 applications).The Enhanced mode of operation allows the full feature set of the N80C186-25 to be used.It is upward compatible with 8086 and 8088 software and fully compatible with 80186 and 80188 software.

The N80C186-25,when in Enhanced mode,can enter a power saving state by internally divingthe processor clock frequency by a programmable factor.This divided frequency is also avaliable at the CLKOUT pin.The PDCON register contains the three-bit fields for selecting the clock division factor and the enable bit.The internal clock of the product being to be divided during the T3 state of the instruction cycle that sets the enable bit.Clearing the enable bit restores full speed in the T3 state of that instruction.

The AMD N80C186-25 is a static design and as such has no minimum clock frequency.