Features: • Combines 74F245 and 74F280A functions in one package• High impedance base input for reduced loading (70mA in high and low states)• Ideal in applications where high output drive and light bus loading are required (IIL is 70mA vs FAST std of 600mA)• 3state buffer ...
N74F657N: Features: • Combines 74F245 and 74F280A functions in one package• High impedance base input for reduced loading (70mA in high and low states)• Ideal in applications where high outp...
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Symbol | Parameter | Conditions | Units | |
VCC | Supply voltage | 0.5 to +7.0 | V | |
VIN | Input voltage | 0.5 to +7.0D | V | |
IIN | Input current | 30 to +5 | mA | |
VOUT | Voltage applied to output in High output state | 0.5 to VCC | V | |
IOUT | Current applied to output in Low output state | A0 A7 | 40 | mA |
B0 B7, PARITY, ERROR | 128 | |||
Tamb | Operating free air temperature range | Commercial range | 0 to +70 | °C |
Industrial range | 40 to +85 | °C | ||
TSTG | Storage temperature | 65 to +150 | °C |
The 74F657 is an octal transceiver featuring noninverting buffers with 3state outputs and an 8bit parity generator/checker, and is intended for busoriented applications. The 74F657 buffers have a guaranteed current sinking capability of 24mA at the A ports and 64mA at the B ports. The transmit/receive (T/R) input determines the direction of the data flow through the bidirectional transceivers.
Transmit (active high) enables data from A ports to B ports; receive (active low) enables data from B ports to A ports. The output enable (OE) input disables both the A and B ports by placing them in a high impedance condition when the OE input is high.The parity select (ODD/EVEN) input gives the user the option of odd or even parity systems.The parity (PARITY) pin of 74F657 is an output from the generator/checker when transmitting from the port A to B (T/R = high) and an input when receiving from port B to A port ( T/R = low).
When transmitting (T/R = high) the parity select (ODD/EVEN) input is set, then the A port data is polled to determined the number of high bits. The parity (PARITY) output then goes to the logic state determined by the parity select (ODD/EVEN) setting and by the number of high bits on port A.For example, if the parity select (ODD/EVEN) of 74F657 is set low (even parity), and the number of high bits on port A is odd, then the parity (PARITY) output will be high, transmitting even parity. If the number of high bits on port A is even, then the parity (PARITY) output will be low, keeping even parity.When in receive mode (T/R = low) the B port is polled to determine the number of high bits. If parity select (ODD/EVEN) is low (even parity) and the number of highs on port B is: (1) odd and the parity (PARITY) input is high, then ERROR will be high, significantly no error.(2) even and the parity (PARITY) input is high, then ERROR will be asserted low, indicating an error.