N74F299D

Counter Type :
Number of Circuits : 1
Packaging : Tube
Logic Type : Bipolar
Maximum Operating Temperature : + 70 C
Minimum Operating Temperature : 0 C
Output Type : 3-State
Counting Sequence : Serial/Parallel to Serial/Parallel
Package / Case : SO
Logic Family : F
Number of Input Lines : 10
Propagation Delay Time : 8 ns


Features:

·Common parallel I/O for reduced pin count
·Additional serial inputs and outputs for expansion
·Four operating modes: Shift left, shift right, load and store
·3-State outputs for bus-oriented applications

 

Pinout




Specifications

 

(Operation beyond the limits set forth in this table may impair the useful life of the device. Unless otherwise noted these limits are over the
operating free-air temperature range.)

SYMBOL	PARAMETER		RATING	UNIT
VCC	Supply voltage		0.5 to +7.0	V
VIN	Input voltage		0.5 to +7.0	V
IIN	Input current		30 to +5	mA
VOUT	Voltage applied to output in High output state		0.5 to VCC	V
IOUT	Current applied to output in Low output state	Q0, Q7	40	mA
		I/On	48	mA
Tamb	Operating free-air temperature range		0 to +70	°C
Tstg	Storage temperature range		65 to +150	°C

Description

The 74F299 is an 8-bit universal shift/storage register with 3-State outputs. Four modes of operation are possible: Hold (store), shift left, shift right and parallel load. The parallel load inputs and flip-flop outputs are multiplexed to reduce the total number of package pins. Additional outputs are provided for flip-flops Q0 and Q7 to allow easy serial cascading. A separate active-Low Master Reset is used to reset the register.
 
The 74F299 contains eight edge-triggered D-type flip-flops and the interstage logic necessary to perform synchronous shift left, shift right, parallel load and hold operations. The type of operation is determined by S0 and S1, as shown in the Function Table. All flip-flop outputs are brought out through 3-State buffers to separate I/O pins that also serve as data inputs in the parallel load mode. Q0 and Q7 are also brought out on other pins for expansion in serial shifting of longer words.

A Low signal on MR  overrides the Select and CP inputs and resets the flip-flops. All other state of 74F299 changes are initiated by the rising edge f the clock. Inputs can change when the clock is in either state provided only that the recommended setup and hold times, relative to the rising edge of clock are observed.

A High signal on either OE 0 or OE1 disables the 3-State buffers and uts the I/O pins in the high impedance state. In this condition the shift, hold, load and reset operations can still occur. The 74F299 3-State buffers are also disabled by High signals on both S0 and S1 in preparation for a parallel load operation.