N74F280BD

Parity Functions 9-BIT ODD/EVEN PAR GEN CHECKER

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N74F280BD Picture
SeekIC No. : 00448306 Detail

N74F280BD: Parity Functions 9-BIT ODD/EVEN PAR GEN CHECKER

floor Price/Ceiling Price

Part Number:
N74F280BD
Mfg:
NXP Semiconductors
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2025/1/8

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Product Details

Quick Details

Number of Circuits : 1 Number of Bits : 9
Logic Family : F Package / Case : SO-14
High Level Output Current : - 1 mA Low Level Output Current : 20 mA
Propagation Delay Time : 10 ns Operating Supply Voltage : 5 V
Maximum Operating Temperature : + 70 C Minimum Operating Temperature : 0 C
Packaging : Tube    

Description

Number of Circuits : 1
Number of Bits : 9
Logic Family : F
High Level Output Current : - 1 mA
Low Level Output Current : 20 mA
Propagation Delay Time : 10 ns
Operating Supply Voltage : 5 V
Maximum Operating Temperature : + 70 C
Minimum Operating Temperature : 0 C
Packaging : Tube
Package / Case : SO-14


Features:

`High-impedance NPN base inputs for reduced loading  (20A in Low and High states)
`Buffered inputs - one normalized loa
`Word length easily expanded by cascading
`Industrial temperature range available (-40to +85)




Pinout

  Connection Diagram


Specifications

SYMBOL
PARAMETER
RATING
UNIT
VCC
Supply voltage
0.5 to +7.0
V
VIN
Input voltage
0.5 to +7.0
V
IIN
Input current
30 to +5
mA
VOUT
Voltage applied to output in High output state
0.5 to VCC
V
IOUT
Current applied to output in Low output state
40
mA
Tamb
Operating free-air temperature range Commercial range
0 to +70
°C
Industrial range
-40 to +85
°C
Tstg
Storage temperature range
65 to +150
°C



Description

The 74F280B is a 9-bit Parity Generator or Checker commonly used to detect errors in high speed data transmission or data retrieval systems. Both Even (E) and Odd (O ) parity outputs are available for generating or checking even or odd parity on up to 9 bits.

The Even (E) parity output of 74F280B is High when an even number of Data inputs (I0- I8) are High. The Odd (o) parity output is High when an odd number of Data inputs are High.

Expansion to larger word sizes is accomplished by tying the Even (E) outputs of up to nine parallel devices to the data inputs of the final stage. This expansion scheme of 74F280B allows an 81-bit data word to be checked in less than 20ns.




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