N74F194

Features:

• Shift right and shift left capability
• Synchronous parallel and serial data transfer
• Easily expanded for both serial and parallel operation
• Asynchronous Master Reset
• Hold (do nothing) mode


Pinout




Description

The functional characteristics of the 74F194 4-Bit Bidirectional Shift Register are indicated in the Logic Diagram and Function Table. The 74F194 register is fully synchronous, with all operations taking place in less than 9ns (typical) for 74F, making the 74F194 especially useful for implementing very high speed CPUs, or for memory buffer registers. The 74F194 design has special logic features which increase the range of application. The synchronous operation of the 74F194 is determined by two Mode Select inputs, S0 and S1. As shown in the Mode Select-Function Table, data can be entered and shifted from left to right (shift right, Q0"Q1, etc.), or right to left (shift left, Q3"Q2, etc.), or parallel data can be entered, loading all 4 bits of the register simultaneously. When both S0 and S1 are Low, existing data is retained in a hold (do nothing) mode. The first and last stages provide D-type Serial Data inputs (DSR, DSL) to allow multistage shift right or shift left data transfers without interfering with parallel load operation. Mode Select and data inputs on the 74F194 are edge-triggered, responding only to the Low-to-High transition of the Clock (CP). Therefore, the only timing restriction is that the Mode Select and selected data inputs must be stable one setup time prior to the Low-to-High transition of the clock pulse. Signals on the Mode Select, Parallel Data (D0D3) and Serial Data (DSR, DSL) can change when the clock is in either state, provided only the recommended setup and hold times, with respect to the clock rising edge, are observed. The four Parallel Data inputs (D0D3) are D-type inputs. Data appearing on (D0D3) inputs when S0 and S1 are High is transferred to the Q0Q3 outputs respectively, following the next Low-to-High transition of the clock. When Low, the asynchronous Master Reset (MR) overrides all other input conditions and forces the Q outputs Low.