N74F173D

The 74F173 is a high speed 4bit parallel load register with clock enable control, 3state buffered outputs, and master reset (MR). When the two clock enable (E0 and E1) inputs are low, the data on the D inputs is loaded into the register simultaneously with lowtohigh clock (CP) transition. When one or both enable inputs are high one setup time before the lowtohigh clock transition, the register retains the previous data.

Data inputs and clock enable inputs of 74F173 are fully edgetriggered and must be stable only one setup time before the lowtohigh clock transition.

The master reset (MR) of 74F173 is an activehigh asynchronous input. When the MR is high, all four flipflops are reset (cleared) independently of any other input condition.

The 74F173 3state output buffers are controlled by a 2input NOR gate. When both output enable (OE0 and OE1) inputs are low, the data in the register is presented at the Q output. When one or both OE inputs are high, the outputs are forced to a high impedance "off" state.

The 74F173 3state output buffers are completely independent of the register operation; the OE transition does not affect the clock and reset operations.