N74F166N

Counter Type :
Output Type :
Number of Circuits : 1
Number of Input Lines : 9
Packaging : Tube
Package / Case : PDIP-16
Logic Type : Bipolar
Maximum Operating Temperature : + 70 C
Minimum Operating Temperature : 0 C
Counting Sequence : Serial/Parallel to Serial/Parallel
Logic Family : F
Propagation Delay Time : 7.5 ns


Features:

• High impedance NPN base inputs for reduced loading
  (20mA in high and low states)
• Synchronous parallel to serial applications
• Synchronous serial data input for easy expansion
• Clock enable for "do nothing" mode
• Asynchronous master reset
• Expandable to 16 bits in 8bit increments
• Industrial temperature range available (40°C to +85°C)


Pinout




Specifications

Symbol	Parameter		Conditions	Units
VCC	Supply voltage		0.5 to +7.0	V
VIN	Input voltage		0.5 to +7.0D	V
IIN	Input current		30 to +5	mA
VOUT	Voltage applied to output in High output state		0.5 to VCC	V
IOUT	Current applied to output in Low output state		40	mA
Tamb	Operating free air temperature range	Commercial range	0 to +70	°C
		Industrial range	40 to +85	°C
TSTG	Storage temperature		65 to +150	°C

Description

The 74F166 is a high speed 8bit shift register that has fully synchronous serial parallel data entry selected by an active low parallel enable (PE) input. When the PE of 74F166 is low one setup time before the lowtohigh clock transition, parallel data is entered into the register.

When PE of 74F166 is high, data is entered into internal bit position Q0 from serial data input (Ds), and the remaining bits are shifted one place to the right (Q0 " Q1 " Q2, etc.) with each positive going clock transition.

For expansion of the 74F166 register in parallel to serial converters, the Q7 output is connected to the Ds input of the succeeding stage. The clock input is gated OR structure which allows one input to be used as an activelow clock enable (CE) input. The pin assignment for the CP and CE inputs is arbitrary and can be reversed for layout convenience. The lowtohigh transition of CE input should only take place while the CP is high for predictable operation. A low on the master reset (MR) input overrides all other inputs and clears the register asynchronously, forcing all bit positions to a low state.