N74F109N

Output Type :
Low Level Output Current :
Package / Case :
Supply Voltage - Max : 5.5 V
Number of Circuits : 2
Input Type : Single-Ended
Mounting Style : Through Hole
Packaging : Tube
Polarity : Inverting/Non-Inverting
Maximum Operating Temperature : + 70 C
Propagation Delay Time : 6.2 ns
Logic Family : F
High Level Output Current : - 1 mA
Logic Type : J-K Positive Edge Triggered Flip Flop


Features:

• Industrial temperature range available (40°C to +85°C)


Pinout




Specifications

Symbol	Parameter		Conditions	Units
VCC	Supply voltage		0.5 to +7.0	V
VIN	Input voltage		0.5 to +7.0D	V
IIN	Input current		30 to +5	mA
VOUT	Voltage applied to output in High output state		0.5 to VCC	V
IOUT	Current applied to output in Low output state		40	mA
Tamb	Operating free air temperature range	Commercial range	0 to +70	°C
		Industrial range	40 to +85	°C
TSTG	Storage temperature		65 to +150	°C

Description

The 74F109 is a dual positive edge-triggered JK-type flip-flop featuring individual J, K, clock, set, and reset inputs; also true and complementary outputs. Set (SD) and reset (RD) are asynchronous active low inputs and operate independently of the clock (CP) input. The J and K are edge-triggered inputs which control the state changes of the 74F109 flip-flops as described in the function table. Clock triggering occurs at a voltage level and is not directly related to the transition time of the positive-going pulse. The J andK inputs must be stable just one setup time prior to the low-to-high transition of the clock for predictable operation. The JK design of 74F109 allows operation as a D flip-flop by tying J and K inputs together. Although the clock input is level sensitive, the positive transition of the clock pulse between the 0.8V and 2.0V levels should be equal to or less than the clock to output delay time for reliable operation.