Features: ·4-Level Root Raised Cosine FSK Modulation· Half Duplex, 4800 to 19.2kbps · Increase Channel Bit Rate/Hz ·Full Data Packet Framing ·Impulse and NRZ Signal Modes · Enhanced Performance in Noisy Conditions · Error Detection and Error Correction ·Low Power 3.3V/5.0V Operation Application ...
MX919B: Features: ·4-Level Root Raised Cosine FSK Modulation· Half Duplex, 4800 to 19.2kbps · Increase Channel Bit Rate/Hz ·Full Data Packet Framing ·Impulse and NRZ Signal Modes · Enhanced Performance in ...
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General |
Min. |
Max. |
Units |
Supply (VDD - VSS) |
-0.3 |
7.0 |
V |
Voltage on any pin to VSS |
-0.3 |
VDD + 0.3 |
V |
Current | |||
VDD |
-30 |
30 |
mA |
VSS |
-30 |
30 |
mA |
Any other pin | -20 |
20 |
mA |
DW, LH, P Package | |||
Total Allowable Power Dissipation at TAMB = 25 |
800 |
mW | |
Derating above 25 |
13 |
mW/ above 25 | |
Storage Temperature |
-55 |
125 |
|
Operating Temperature |
-40 |
85 |
|
DS Package | |||
Total Allowable Power Dissipation at TAMB = 25 |
550 |
mW | |
Derating above 25 |
9 |
mW/ above 25 | |
Storage Temperature |
-55 |
125 |
|
Operating Temperature |
-40 |
85 |
The MX919B is a low voltage CMOS device containing all of the baseband signal processing and Medium Access Control (MAC) protocol functions required for a high performance 4-level FSK Wireless Packet Data Modem. It interfaces with the modem host C and the radio modulation/demodulation circuits to deliver reliable two-way transfer of the application data over a wireless link.
The MX919B assembles application data received from the host C, adds forward error correction (FEC) and error detection (CRC) information, and interleaves the result for burst-error protection. After automatically adding symbol and frame sync codewords, the data packet is converted into filtered 4-level analog signals for modulating the radio transmitter.
In receive mode, the MX919B performs the reverse function using the analog signals from the receiver discriminator. After error correction and removal of the packet overhead, the recovered application data is supplied to the host C. CRC detected residual uncorrected data errors will be flagged. A readout of the SNR value during receipt of a packet is also provided.
The MX919B uses data block sizes and FEC/CRC suitable for applications where high-speed transfer of data over narrow-band wireless links is required. The device is programmable to operate at standard bit rates from a wide range of Xtal/clock frequencies.
The MX919B may be used with a 3.0V to 5.5V power supply and is available in the following package styles: 24-pin SSOP (MX919BDS), 24-pin SOIC (MX919BDW), 24-pin PLCC (MX919BLH), and 24-pin PDIP (MX919BP).