MX7672PK05

The MX7672PK05 is one member of the MX7672 series.The MX7672 is a 12-bit, high-speed, BiCMOS, analog-to-digital converter (ADC) that performs conversions in as little as 3s while consuming only 110mW of power.The MX7672 is a plug-in replacement for AD7672.The MX7672 requires an external -5V reference.A buffered reference input minimizes reference current requirements and allows a single reference to drive several ADCs.External reference specifications can be chosen to suit the accuracy of the application.The ADC clock can be driven from either a crystal or an external clock source, such as a microprocessor (P) clock.

Features of the MX7672PK05 are:(1)operates with +5V and -12V Supplies; (2)buffered reference input; (3)low 110mW power consumption; (4)choice of +5V,±10V or ±5V input ranges; (5)fast 125ns bus-access time; (6)plug-in replacement for AD7672; (7)12-bit resolution and accuracy.Analog input range is pin-selectable for 0 to +5V, 0 to +10V, or ±5V, making the ADC ideal for data-acquisition and analog input/output cards.A high-speed digital interface (125ns data-access time) with three-state data outputs is compatible with most Ps.

The absolute maximum ratings of the MX7672PK05 can be summarized as:(1)Vdd to DGND:0.3 V to 7 V;(2)Vss to DGND:+0.3 V to -17 V;(3)AGND to DGND:0.3 V to Vdd+0.3 V;(4)storage temperature:-65 to 150;(5)lead temperature:300;(6)continuous power dissipation:100 mW.The ROM mode avoids placing the P into a wait state.A conversion begins with a read operation. While CS and RD are low, data from the last conversion is available on the data outputs. A second read operation reads the new data and begins the conversion process again.A delay at least as long as the MX7672 conversion time must be allowed between read operations. The data on the output bus is in a parallel format in either mode.If the data bus connected to the ADC is active during a conversion, coupling from the data pins to the ADC comparator may cause LSBs of error.  Using slow-memory mode avoids this problem by placing the P into a wait state during the conversion.In ROM mode, if the data bus is active during the conversion,use three-state drivers to isolate the bus from the ADC.