Features: • Extended single - supply voltage range 2.7V to 3.6V• 2,097,152 x 8/1,048,576 x 16 switchable• Single power supply operation- 3.0V only operation for read, erase and program operation• Fast access time: 70/90ns• Low power consumption- 20mA maximum active cu...
MX29LV161T: Features: • Extended single - supply voltage range 2.7V to 3.6V• 2,097,152 x 8/1,048,576 x 16 switchable• Single power supply operation- 3.0V only operation for read, erase and pro...
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Features: SpecificationsDescription The MX29F001T/B is a 1-mega bit Flash memory organized as 128K...
The MX29LV161T/B is a 16-mega bit Flash memory organized as 2M bytes of 8 bits or 1M words of 16 bits.MXIC's Flash memories offer the most cost-effective and reliable read/write non-volatile random access memory. The MX29LV161T/B is packaged in 44-pin SOP, 48-pin TSOP, and 48CSP. It is designed to be reprogrammed and erased in system or in standard EPROM programmers.
The standard MX29LV161T/B offers access time as fast as 70ns, allowing operation of high-speed microprocessors
without wait states. To eliminate bus contention,the MX29LV161T/B has separate chip enable (CE) and output enable (OE) controls.
MXIC's Flash memories augment EPROM functionality with in-circuit electrical erasure and programming.The MX29LV161T/B uses a command register to manage this functionality. The command register allows for 100% TTL level control inputs and fixed power supply levels during erase and programming, while maintaining maximum EPROM compatibility.
MXIC Flash technology reliably stores memory contents even after 100,000 erase and program cycles. The MXIC cell is designed to optimize the erase and programming mechanisms. In addition, the combination of advanced tunnel oxide processing and low internal electric fields for erase and program operations produces reliable cycling.The MX29LV161T/B uses a 2.7V~3.6V VCC supply to perform the High Reliability Erase and auto Program/ Erase algorithms.
The highest degree of latch-up protection is achieved with MXIC's proprietary non-epi process. Latch-up protection
is proved for stresses up to 100 milliamps on address and data pin from -1V to VCC + 1V.