Features: • Ready/Busy# pin (RY/BY#) - Provides a hardware method of detecting program or erase operation completion.• Sector protection - Hardware method to disable any combination of sectors from program or erase operations - Temporary sector unprotect allows code changes in previous...
MX29LV002C: Features: • Ready/Busy# pin (RY/BY#) - Provides a hardware method of detecting program or erase operation completion.• Sector protection - Hardware method to disable any combination of s...
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Features: SpecificationsDescription The MX29F001T/B is a 1-mega bit Flash memory organized as 128K...
The MX29LV002C T/B is a 2-mega bit Flash memory organized as 256K bytes of 8 bits. MXIC's Flash memories offer the most cost-effective and reliable read/write non-volatile random access memory. The MX29LV002C T/B is packaged in 32-pin TSOP and 32-pin PLCC. It is designed to be reprogrammed and erased in system or in standard EPROM programmers.
The standard MX29LV002C T/B offers access time as fast as 70ns, allowing operation of high-speed microprocessors without wait states. To eliminate bus contention, the MX29LV002C T/B has separate chip enable (CE#) and output enable (OE#) controls.
MXIC's Flash memories augment EPROM functionality with in-circuit electrical erasure and programming. The MX29LV002C T/B uses a command register to manage this functionality. The command register allows for 100%
TTL level control inputs and fixed power supply levels during erase and programming, while maintaining maximum EPROM compatibility.
MXIC Flash technology reliably stores memory contents even after 100,000 erase and program cycles. The MXIC cell is designed to optimize the erase and programming mechanisms. In addition, the combination of advanced tunnel oxide processing and low internal electric fields for erase and program operations produces reliable cycling. The MX29LV002C T/B uses a 2.7V~3.6V VCC supply to perform the High Reliability Erase and auto Program/Erase algorithms.
The highest degree of latch-up protection is achieved with MXIC's proprietary non-epi process. Latch-up protection is proved for stresses up to 100 milliamps on address and data pin from -1V to VCC + 1V.