MX29L8100G

The MX29L8100G is a 8 Mbit, 3.3 V-only Flash memory organized as a either 1 Mbytesx8 or 512K word x16. For flexible erase and program capability, the 8 Mbits of data is divided into 11 sectors of one 16 Kbyte block, two 8 Kbyte parameter blocks, one 96 Kbyte main block, and seven 128 Kbyte main blocks. To allow for simple insystem operation, the device can be operated with a single 3.0 V to 3.6 V supply voltage. Since many designs read from the flash memory a large percentage of the time, significant power saving is achieved with the 3.0 V VCC Operation.

The MX29L8100G command set is compatible with the JEDEC single-power-supply flash standard. Commands are written to the command register using standard microprocessor write timings. MXIC's flash memory augments EPROM functionality with an internal state machine which controls the erase and program circuitry. The device Status Register provides a convenient way to monitor when a program or erase cycle is complete, and the success or failure of that cycle.

Programming the MX29L8100G is performed on a page basis; 128 bytes of data are loaded into the device and then programmed simultaneously. The typical Page Pro-gram time is 5ms.The device can also be reprogrammed in standard EPROM programmers. Reading data out of the device is similar to reading from an EPROM or other flash.

Erase is accomplished by executing the Erase command sequence. This will invoke the Auto Erase algorithm which is an internal algorithm that automatically times the erase pulse widths and verifies proper cell margin. This device features both chip erase and block erase. Each block can be erased and programmed without affecting other blocks. Using MXIC's advanced design technology, no preprogram is required (internally or externally). As a result, the whole chip can be typically erased and verified in as fast as 50 ms.

The MX29L8100G has 128 Bytes built-in page buffer, which can serve as SRAM. This feature provides a convenient way to store temporary data for fast read and write.

The highest degree of latch-up protection is achieved with MXIC's proprietary non-epi process. Latch-up protection is proved for stresses up to 100 milliamps on address and data pin from -1V to VCC +1V.