MX29L8000B

The MX29L8000T/MX29L8000B is a 8 Mbit, 3 V-only Flash memory organized as a 1 Mbytes of 8 bits each. For flexible erase and program capability, the 8 Mbits of data is divided into 11 sectors of one 16 Kbyte protected block, two 8 Kbyte parameter blocks, one 96 Kbyte main block, and seven 128 Kbyte main blocks. To allow for simple in-system operation, the device can be operated with a single 2.7 V to 3.6 V supply voltage. Since many designs read from the flash memory a large percentage of the time,significant power saving is achieved with the 2.7 V VCC operation. Manufactured with MXIC's advanced nonvolatile memory technology, the device offers access times of 120 ns, and a low 1uA typical deep power-down current.

The MX29L8000T/MX29L8000B command set is compatible with the JEDEC single-power-supply flash standard. Commands are written to the command register using standard microprocessor write timings. MXIC's flash memory augments EPROM functionality with an internal state machine which controls the erase and program circuitry.The device Status Register provides a convenient way to monitor when a program or erase cycle is complete, and the success or failure of that cycle.

Programming the MX29L8000T/MX29L8000B is performed on a page basis; 128 bytes of data are loaded into the device and then programmed simultaneously. The typical Page Program time is 5ms.The device can also be reprogrammed in standard EPROM programmers.Reading data out of the device is similar to reading from an EPROM or other flash.

Erase is accomplished by executing the Erase command sequence. This will invoke the Auto Erase algorithm which is an internal algorithm that automatically times the erase pulse widths and verifies proper cell margin. This device features both chip erase and block erase. Each block can be erased and programmed without affecting other blocks. Using MXIC's advanced design technology, no preprogram is required (internally or externally). As a result, the whole MX29L8000B can be typically erased and verified in as fast as 50 ms.

A combined feature of Write Protection pin (WP), Reset pin (RP), 16K-block lockout bit, and software command sequences provides complete data protection. First,software data protection protects the device from inadvertent program or erase. Two "unlock" write cycles must be presented to the device before the program or erase command can be accepted by the device. For hardware data protection, the WP pin and RP pin provide protection against unwanted command writes due to invalid system bus condition that may occur during system reset and power-up/down sequence. Finally, with 16K-block lockout bit feature, the MX29L8000B provides complete core security for the kernel code required for system initialization.