Features: • 3.3V ± 10% write, erase and read• Endurance: 10,000 cycles• Fast random access time: 100ns/120ns• Fast pagemode access time: 50ns• Page access depth: 16 bytes/8 words• Sector erase architecture- 32 equal sectors of 64K word each- Sector erase time: 2...
MX29L3211: Features: • 3.3V ± 10% write, erase and read• Endurance: 10,000 cycles• Fast random access time: 100ns/120ns• Fast pagemode access time: 50ns• Page access depth: 16 byt...
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Features: SpecificationsDescription The MX29F001T/B is a 1-mega bit Flash memory organized as 128K...
The MX29L3211 is a 32-mega bit pagemode Flash memory organized as either 4M word x 8 or 2M byte x 16. The MX29L3211 includes 32 sectors of 64K words. MXIC's Flash memories offer the most cost-effective and reliable read/write non-volatile random access memory and fast page mode access.
The MX29L3211 is packaged 44-pin SOP and 48-pin TSOP. It is designed to be reprogrammed and erased in-system or in-standard EPROM programmers. The standard MX29L3211 offers access times as fast as 100ns,allowing operation of high-speed microprocessors without wait. To eliminate bus contention, the MX29L3211 has separate chip enable CE, output enable (OE), and write enable (WE) controls. MXIC's Flash memories augment EPROM functionality with in-circuit electrical erasure and programming.
The MX29L3211 uses a command register to manage this functionality. To allow for simple in-system reprogrammability, the MX29L3211 does not require high input voltages for programming. Three-volt-only commands determine the operation of the device. Reading data out of the device is similar to reading from an EPROM. MXIC Flash technology reliably stores memory contents even after 10,000 cycles. The MXIC's cell is designed to optimize the erase and programming mechanisms.
In addition, the combination of advanced tunnel oxide processing and low internal electric fields for erase and programming operations produces reliable cycling.
The MX29L3211 uses a 3.3V ± 10% VCC supply to perform the Auto Erase and Auto Program algorithms. The highest degree of latch-up protection is achieved with MXIC's proprietary non-epi process. Latch-up protection is proved for stresses up to 100 milliamps on address and data pin from -1V to VCC +1V.