Features: GENERAL FEATURES
• Power Supply Operation
- 2.7 to 3.6 volt for read, erase, and program operations
- V I/O voltage must tight with VCC
- VI/O=VCC=2.7V~3.6V
• Byte/Word mode switchable
- 33,554,432 x 8 / 16,777,216 x 16 (MX29GL256E H/L)
- 16,777,216 x 8 / 8,388,608 x 16 (MX29GL128E H/L)
• 64KW/128KB uniform sector architecture
- MX29GL256E H/L: 256 equal sectors
- MX29GL128E H/L: 128 equal sectors
• 16-byte/8-word page read buffer
• 64-byte/32-word write buffer
• Extra 128-word sector for security
- Features factory locked and identifiable, and customer lockable
• Advanced sector protection function (Persifent and Password Protect)
• Latch-up protected to 100mA from -1V to 1.5xVcc
• Low Vcc write inhibit : Vcc VLKO
• Compatible with JEDEC standard
- Pinout and software compatible to single power supply Flash
• Deep power down mode
PERFORMANCE
• High Performance
- Fast access time:
- MX29GL256E H/L: 100ns (VCC=2.7~3.6V), 90ns (VCC=3.0~3.6V)
- MX29GL128E H/L: 90ns (VCC=2.7~3.6V)
- Page access time: 25ns
- Fast program time: 11us/word
- Fast erase time: 0.6s/sector
• Low Power Consumption
- Low active read current: 30mA (typical) at 5MHz
- Low standby current: 30uA (typical)
• Typical 100,000 erase/program cycle
• 10 years data retention
SOFTWARE FEATURES
• Program/Erase Suspend & Program/Erase Resume
- Suspends sector erase operation to read data from or program data to another sector which is not being erased
- Suspends sector program operation to read data from another sector which is not being program
• Status Reply
- Data# Polling & Toggle bits provide detection of program and erase operation completion
• Support Common Flash Interface (CFI)
HARDWARE FEATURES
• Ready/Busy# (RY/BY#) Output
- Provides a hardware method of detecting program and erase operation completion
• Hardware Reset (RESET#) Input
- Provides a hardware method to reset the internal state machine to read mode
• WP#/ACC input pin
- Hardware write protect pin/Provides accelerated program capability
PACKAGE
• 56-Pin TSOP
• 64-Ball FBGA (10mm x 13mm)
• 64-Ball LFBGA (11mm x 13mm)
• 70-Pin SSOP
• All Pb-free devices are RoHS CompliantPinout
SpecificationsDescriptionThe block diagram on Page 4 illustrates a simplified architecture of this device. Each block in the block diagram represents one or more circuit modules in the real MX29GL256EH used to access, erase, program, and read the memory array.
The "CONTROL INPUT LOGIC" block receives input pins CE#, OE#, WE#, RESET#, BYTE#, and WP#/ACC. MX29GL256EH creates internal timing control signals according to the input pins and outputs to the "ADDRESS LATCH AND BUFFER" to latch the external address pins A0-AM(A23). The internal addresses are output from this block to the main array and decoders composed of "X-DECODER", "Y-DECODER", "Y-PASS GATE", AND "FLASH ARRAY". The X-DECODER decodes the word-lines of the flash array, while the Y-DECODER decodes the bit-lines of the flash array. The bit lines are electrically connected to the "SENSE AMPLIFIER" and "PGM DATA HV" selectively through the Y-PASS GATES. SENSE AMPLIFIERS are used to read out the contents of the flash memory, while the "PGM DATA HV" block is used to selectively deliver high power to bit-lines during programming. The "I/O BUFFER" controls the input and output on the Q0-Q15/A-1 pads. During read operation, the I/O BUFFER receives data from SENSE AMPLIFIERS and drives the output pads accordingly. In the last cycle of program command, the I/O BUFFER transmits the data on Q0-Q15/A-1 to "PROGRAM DATA LATCH", which controls the high power drivers in "PGM DATA HV" to selectively program the bits in a word or byte according to the user input pattern.
The "PROGRAM/ERASE HIGH VOLTAGE" block comprises the MX29GL256EH to generate and deliver the necessary high voltage to the X-DECODER, FLASH ARRAY, and "PGM DATA HV" blocks. The logic control module comprises of the "WRITE STATE MACHINE, WSM", "STATE REGISTER", "COMMAND DATA DECODER", and "COMMAND DATA LATCH". When the user issues a command by toggling WE#, the command on Q0-A15/A-1 is latched in the COMMAND DATA LATCH and is decoded by the COMMAND DATA DECODER. The STATE REGISTER receives the command and records the current state of the device. The WSM implements the internal algorithms for program or erase according to the current command state by controlling each block in the block diagram.
MX29GL256EH Data Sheet
