MX29F800T

• 1,048,576 x 8/524,288 x 16 switchable
• Single power supply operation
  - 5.0V only operation for read, erase and program operation
• Fast access time: 70/90/120ns
• Low power consumption
  - 50mA maximum active current
  - 0.2uA typical standby current
• Command register architecture
  - Byte/word Programming (7us/12us typical)
  - Sector Erase (Sector structure 16K-Bytex1, 8K-Bytex2, 32K-Bytex1, and 64K-Byte x15)
• Auto Erase (chip & sector) and Auto Program
  - Automatically erase any combination of sectors with Erase Suspend capability.
  - Automatically program and verify data at specified address
• Erase suspend/Erase Resume
  - Suspends sector erase operation to read data from, or program data to, another sector that is not being erased, then resumes the erase.
• Status Reply
  - Data polling & Toggle bit for detection of program and erase operation completion.
• Ready/Busy pin (RY/BY)
  - Provides a hardware method of detecting program or erase operation completion.
• Sector protection
  - Sector protect/chip unprotect for 5V/12V system.
  - Hardware method to disable any combination of sectors from program or erase operations
  - Tempory sector unprotect allows code changes in previously locked sectors.
• 100,000 minimum erase/program cycles
• Latch-up protected to 100mA from -1V to VCC+1V
• Boot Code Sector Architecture
  - T = Top Boot Sector
  - B = Bottom Boot Sector
• Low VCC write inhibit is equal to or less than 3.2V
• Package type:
  - 44-pin SOP
  - 48-pin TSOP
• Compatibility with JEDEC standard
  - Pinout and software compatible with single-power supply Flash

The MX29F800T/B is a 8-mega bit Flash memory organized as 1M bytes of 8 bits or 512K words of 16 bits. MXIC's Flash memories offer the most cost-effective and reliable read/write non-volatile random access memory. The MX29F800T/B is packaged in 44-pin SOP, 48-pin TSOP. It is designed to be reprogrammed and erased in system or in standard EPROM programmers.

The standard MX29F800T/B offers access time as fast as 70ns, allowing operation of high-speed microprocessors without wait states. To eliminate bus contention, the MX29F800T/B has separate chip enable (CE) and output enable (OE) controls.

MXIC's Flash memories augment EPROM functionality with in-circuit electrical erasure and programming. The MX29F800T/B uses a command register to manage this functionality. The command register allows for 100%TTL level control inputs and fixed power supply levels during erase and programming, while maintaining maximum EPROM compatibility.

MXIC Flash technology reliably stores memory contents even after 100,000 erase and program cycles. The MXIC cell is designed to optimize the erase and programming mechanisms. In addition, the combination of advanced tunnel oxide processing and low internal electric fields for erase and program operations produces reliable cycling. The MX29F800T/B uses a 5.0V±10% VCC supply to perform the High Reliability Erase and auto Program/ Erase algorithms.

The highest degree of latch-up protection is achieved with MXIC's proprietary non-epi process. Latch-up protection is proved for stresses up to 100 milliamps on address and data pin from -1V to VCC + 1V.