Features: • Extended single - supply voltage range 3.0V to 3.6V• 524,288 x 8/262,144 x 16 switchable• Single power supply operation- 3.0V only operation for read, erase and program operation• Fast access time: 55/70ns• Low power consumption- 30mA maximum active curren...
MX26LV400: Features: • Extended single - supply voltage range 3.0V to 3.6V• 524,288 x 8/262,144 x 16 switchable• Single power supply operation- 3.0V only operation for read, erase and program...
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Features: • 128K x 8 organization• +5V operating power supply• +12.75V program/e...
The MX26LV400 is a 4-mega bit high speed Flash memory organized as 512K bytes of 8 bits or 256K words of 16 bits. MXIC's high speed Flash memories offer the most cost-effective and reliable read/write non-volatile random access memory. The MX26LV400 is packaged in 48-pin TSOP, and 48-ball CSP. It is designed to be reprogrammed and erased in system or in standard EPROM programmers.
The standard MX26LV400 offers access time as fast as 55ns, allowing operation of high-speed microprocessors without wait states. To eliminate bus contention, the MX26LV400 has separate chip enable (CE#) and output enable (OE#) controls.
MXIC's high speed Flash memories augment EPROM functionality with in-circuit electrical erasure and programming. The MX26LV400 uses a command register to manage this functionality. The command register allows for 100% TTL level control inputs and fixed power supply levels during erase and programming, while maintaining maximum EPROM compatibility.
MXIC high speed Flash technology reliably stores memory contents even after 2,000 erase and program cycles. The MXIC cell is designed to optimize the erase and programming mechanisms. In addition, the combination of advanced tunnel oxide processing and low internal electric fields for erase and program operations produces reliable cycling. The MX26LV400 uses a 3.0V~3.6V VCC supply to perform the High Reliability Erase and auto Program/Erase algorithms.
The highest degree of latch-up protection is achieved with MXIC's proprietary non-epi process. Latch-up protection is proved for stresses up to 100 milliamperes on address and data pin from -1V to VCC + 1V.