MT9VDDT3272A - 256MB

Stresses greater than those listed may causepermanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions forextended periods may affect reliability.
Voltage on VDD Supply
Relative to VSS . . . . . . . . . . . . . . . . . . . . -1V to +3.6V
Voltage on VDDQ Supply
Relative to VsSS . . . . . . . . . . . . . . . . . . . -1V to +3.6V
Voltage on VREF and Inputs
Relative to VSS . . . . . . . . . . . . . . . . . . . . -1V to +3.6V
Voltage on I/O Pins
Relative to VSS . . . . . . . . . . . .      -0.5V to V_^DDQ +0.5V
Operating Temperature,
TA (ambient) . . . . . . . . . . . . . . . . . . . . . 0°C to +70
Storage Temperature (plastic) . . . . . .-55°C to +150
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . .  .  9W
Short Circuit Output Current. . . . . . . . . . . . . . . .   50mA

The MT9VDDT3272A - 256MB are high-speed CMOS, dynamic random-access, 128MB and 256MB memory modules organized in a x72 (ECC) configuration. These modules use internally configured quad-bank DDR SDRAM devices.

These DDR SDRAM modules MT9VDDT3272A - 256MB use a double data rate architecture to achieve high-speed operation. The double data rate architecture is essentially a 2nprefetch architecture with an interface designed to transfer two data words per clock cycle at the I/O pins. A single read or write access for the DDR SDRAM module MT9VDDT3272A - 256MB effectively consists of a single 2n-bit wide, oneclock- cycle data transfer at the internal DRAM core and two corresponding n-bit wide, one-half-clockcycle data transfers at the I/O pins.

A bidirectional data strobe (DQS) of MT9VDDT3272A - 256MB is transmitted externally, along with data, for use in data capture at the receiver. DQS is an intermittent strobe transmitted by the DDR SDRAM during READs and by the memory controller during WRITEs. DQS is edge-aligned with data for READs and center-aligned with data for WRITEs.

These DDR SDRAM modules MT9VDDT3272A - 256MB operate from a differential clock (CK and CK#); the crossing of CK going HIGH and CK# going LOW will be referred to as the positive edge of CK. Commands (address and control signals) are registered at every positive edge of CK. Input data of MT9VDDT3272A - 256MB is registered on both edges of DQS, and output data is referenced to both edges of DQS, as well as to both edges of CK.

Read and write accesses to the DDR SDRAM modules MT9VDDT3272A - 256MB are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of an ACTIVE command, which is then followed by a READ or WRITE command. The address bits registered coincident with the ACTIVE command are used to select the device bank and row to be accessed (BA0, BA1 select device bank; A0A11 select device row for the 128MB module, A0A12 select device row for the 256MB module). The address bits of MT9VDDT3272A - 256MB registered coincident with the READ or WRITE command are used to select the device bank and the starting device column location for the burst access.

These DDR SDRAM modules MT9VDDT3272A - 256MB provide for programmable READ or WRITE burst lengths of 2, 4, or 8 locations. An auto precharge function may be enabled to provide a self-timed row precharge that is initiated atthe end of the burst access.

As with standard SDR SDRAM modules, the pipelined, multibank architecture of DDR SDRAM modules MT9VDDT3272A - 256MB allows for concurrent operation, thereby providing high effective bandwidth by hiding row precharge and activation time.

An auto refresh mode  of MT9VDDT3272A - 256MB is provided, along with a powersaving power-down mode. All inputs are compatible with the JEDEC Standard for SSTL_2. All outputs are SSTL_2, Class II compatible. For more information regarding DDR SDRAM operation, refer to the 128Mb and 256Mb DDR SDRAM component data sheet.