Features: • Combined PCM 30 framer, Line Interface Unit (LIU) and link controllers in a 68 pin PLCC or 100 pin MQFP package• Selectable bit rate data link access with optional Sa bits HDLC controller (HDLC0) and channel 16 HDLC controller (HDLC1)• Enhanced performance monitoring ...
MT9075A: Features: • Combined PCM 30 framer, Line Interface Unit (LIU) and link controllers in a 68 pin PLCC or 100 pin MQFP package• Selectable bit rate data link access with optional Sa bits HD...
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• Combined PCM 30 framer, Line Interface Unit (LIU) and link controllers in a 68 pin PLCC or 100 pin MQFP package
• Selectable bit rate data link access with optional Sa bits HDLC controller (HDLC0) and channel 16 HDLC controller (HDLC1)
• Enhanced performance monitoring and programmable error insertion functions
• Low jitter DPLL for clock generation
• Operating under synchronized or free run mode
• Two-frame receive elastic buffer with controlled slip direction indication
• Selectable transmit or receive jitter attenuator
• Intel or Motorola non-multiplexed parallel microprocessor interface
• CRC-4 updating algorithm for intermediate path points of a message-based data link application
• ST-BUS/GCI 2.048 Mbit/s backplane bus for both data and signalling.