Features: • Meets requirements of GR-253-CORE for SONET Stratum 3 and SONET minimum clock• Meets requirements of GR-1244-CORE Stratum 3• Meets requirements of G.813 Option 1 and Option 2 for SDH Equipment Clocks (SEC) with external jitter attenuator• Provides OC-3/STM-1, DS...
MT90401AB1: Features: • Meets requirements of GR-253-CORE for SONET Stratum 3 and SONET minimum clock• Meets requirements of GR-1244-CORE Stratum 3• Meets requirements of G.813 Option 1 and Op...
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Parameter | Symbol | Min | Max | Units | |
1 | Supply Voltage | VDDR | -0.3 | 7.0 | V |
2 | Voltage on any pin | VPIN | -0.3 | VDD+0.3 | V |
3 | Current on any pin | IPIN | 30 | mA | |
4 | Storage temperature | TST | -55 | 125 | |
5 | 80 LQFP package power dissipation | PPD | 1000 | mW |
The MT90401AB1 is a digital phase locked loop (DPLL) that is designed to synchronize SDH (Synchronous Digital Hierarchy) and SONET (Synchronous Optical Network) networking equipment. The MT90401AB1 is used to ensure that the timing of outgoing signals remains within the limits specified by Telcordia, ANSI and the ITU during normal operation and in the presence of disturbances on the incoming synchronization signals.