Features: • Supports unframed serial streams up to 10 Mb/s per T1/E1 or DSL link• Single chip ATM TC (Transmission Convergence) processor• Versatile TDM Interface compatible with most popular T1, E1 or DSL framers• Supports primary rate ISDN lines and Fractional T1/E1•...
MT90225: Features: • Supports unframed serial streams up to 10 Mb/s per T1/E1 or DSL link• Single chip ATM TC (Transmission Convergence) processor• Versatile TDM Interface compatible with m...
SeekIC Buyer Protection PLUS - newly updated for 2013!
268 Transactions
All payment methods are secure and covered by SeekIC Buyer Protection PLUS.
Parameter | Symbol | Min | Max | Units | |
1 | Supply Voltage (2.5 volt core) Supply Voltage (3.3 volt core) Supply Voltage (5.0 volt I/O) |
V2.5 V3.3 VDD5 |
-0.3 -0.3 -1.0 |
3.1 3.9 6.5 |
V |
2 | Voltage at Digital Inputs (VDD5 connected to 3.3V) Voltage at Digital Inputs (VDD5 connected to 5.0V |
VI3.3 VI5.0 |
-1.0 -1.0 |
3.9 6.5 |
V |
3 | Current at Digital Inputs | II | -10 | 10 | A |
4 | Storage Temperature | TST | -40 | 125 | °C |
The MT90225/226 device is targeted to systems implementing TC or UNI (User Network Interface) specifications for T1/E1 rates or DSL rates. In the MT90225/226 architecture, up to 16/8 physical and independent serial links can be terminated through the utilization of off-the-shelf, traditional T1/E1/J1 framers/LIUs and DSL chip sets.
The MT90225/226 device provides ATM system designers with a flexible architecture when implementing ATM access over existing trunk interfaces, allowing a migration towards ATM service technology. The MT90225/226 is compliant with ATM TC/UNI specifications for T1/E1 rates. The MT90225/226 can be configured to operate in different TDM modes to facilitate the implementation of ATM over T1/E1/DSL at both CPE and Central Office sites. The device allows for bandwidth scaleability through the use of the UTOPIA MPHY, Level 1 and Level 2 specification at rates up to 52Mhz.
Main functions that are implemented in the MT90225/226 device are:
• Utopia Level 1 or 2 PHY Interface
• Incoming HEC verification and correction (optional),
• Generation of a new HEC byte
• Format outgoing bytes into multi-vendor TDM formats
• Retrieve ATM Cells from the incoming multi-vendor TDM format
• Perform cell delineation
• Provide various counters to assist in performance monitoring
• Generation and insertion of Idle Cells; The Idle cells are pre-defined.
• Provide structured Interrupt scheme to report various events
• 16-bit microprocessor interface (adaptable to Intel or Motorola interfaces)
• loopbacks