Features: • Cost effective, single chip, 4-port ATM IMA and UNI processor
• Up to 4 IMA groups over 4 T1/E1 links can be implemented
• Supports MIXED mode; links not assigned to an IMA group can be used in UNI mode
• Versatile PCM Interface to most popular T1 or E1 framers, reducing development time
• Supports Symmetrical and Asymmetrical Operation
• Supports both Common Transmit Clock (CTC) and Independent Transmit Clock (ITC) clocking modes
• Supports T1 ISDN lines
• Provides UTOPIA Level 2 MPHY Interface (MT90221 device slaved to ATM device)
• Complies with ITU G.804 recommendations for performing cell mapping into T1 and E1 transmission systems
• Provides ATM framing using cell delineation according to the ITU I.432 cell delineation process
• Provides Header Error Control (HEC) verification and generation, error detection, Filler cell filtering (IMA mode) and Idle/Unassigned cell filtering (UNI mode)
• Provides statistics to support MIB
• Connects to popular asychronous SRAM
• Provides statistics on the number of HEC errors
• 8 bit Microprocessor Interface, compatible with Intel and Motorola
• 3.3V operation / 5V tolerant inputs
• MQFP-208 pin
• JTAG Test supportApplication• Cost effective single chip solution to implement IMA and UNI links over T1 or E1 in all public or private UNI, NNI and B-ICI applications
• ATM Edge switch IMA and UNI Line Card Design
• Can be used for cost reduction in current applications based on FPGA implementation
Pinout
Specifications
| |
Parameter |
Symbol |
Min |
Max |
Units |
| 1 |
Supply Voltage |
VDD |
-0.3 |
3.9 |
V |
| 2 |
Voltage at Digital Inputs |
VI |
-1.0 |
6.5 |
V |
| 3 |
Current at Digital Inputs |
VI |
-10 |
10 |
mA |
| 4 |
Storage Temperature |
TST |
-40 |
125 |
|
* Exceeding these values may cause permanent damage. Functional Operation under these conditions is not implied.
Note: Input pins are 5 Volt compatible typeDescriptionThe MT90221 device is targeted to systems implementing the ATM FORUM UNI specifications for T1/E1 rates or Inverse Multiplexing for ATM (IMA). In the MT90221 architecture, up to 4 physical and independent T1/E1 streams can be terminated through the utilization of off-the-shelf, traditional T1/ E1 framers and LIUs. This allows ATM designers to leverage previous T1/E1 design experience, hardware and software implementation, and to select the best T1/E1 framer for the required application.
The MT90221 device provides ATM system designers with a flexible architecture when implementing ATM access over existing and deployed trunk interfaces, allowing a migration towards ATM service technology. In addition to allowing for the design of ATM UNI specifications for T1/E1 rates, the MT90221 device is compliant with the ATM FORUM IMA specifications for controlling IMA groups of up to 4 trunks in a single chip. The MT90221 can be configured to operate in different modes to facilitate the implementation of the IMA function at both CPE and Central Office sites. For systems targeting ATM over T1/E1 with IMA and UNI operating simultaneously, the MT90221 device provides the ideal architecture and capabilities.
The MT90221 provides up to 4 internal IMA circuits and allows for bandwidth scaleability through the use of the UTOPIA MPHY, Level 2 specification at 25Mhz.
The implementation of the IMA as per AF-PHY- 0086.001 Inverse Multiplexing for ATM (IMA) Specification Version 1.1 is divided into hardware and software functions. Hardware functions are implemented in the MT90221 device and software functions are implemented by the user. Additional hardware functions are included to assist in the collection of statistical information to support MIB implementation.
Hardware functions that are implemented in the MT90221 device are:
• Utopia Level 2 PHY Interface
• Incoming HEC verification and correction (optional),
• Generation of a new HEC byte
• Format outgoing bytes into multi-vendor PCM formats
• Retrieve ATM Cells from the incoming multivendor PCM format
• Perform cell delineation
• Provide various counters to assist in performance monitoring
Hardware functions that are implemented by the IMA processor in the MT90221 device are:
• Transmit scheduler (one per IMA group)
• Generation of the TX IMA Data Cell Rate
• Generation and insertion of ICP cells, Filler Cells and Stuff Cells in IMA mode and Idle Cells in UNI (non-IMA) mode; the ICP cells are programmed by the user and the Filler and Idle cells are pre-defined
• Retrieve and process ICP cells in IMA Mode
• Perform IMA Frame synchronization
• Management of RX links to be part of the internal re-sequencer when active
• Extraction of RX IMA Data Cell Rate
• Verification of delays between links
• Perform re-sequencing of ATM cells using external asynchronous Static RAM
• Can accommodate more than 400 msec of link differential delay depending on the amount of external memory
• Provide structured Interrupt scheme to report various events.
MT90221 Data Sheet
