MT8941BP

The MT8941BP  is a dual digital phase-locked loop providing the timing and synchronization signals for the T1 or CEPT transmission links and the ST-BUS.The first PLL provides the T1 clock (1.544 MHz) synchronized to the input frame pulse at 8 kHz. The timing signals for the CEPT transmission link and the ST-BUS are provided by the second PLL locked to an internal or an external 8 kHz frame pulse signal.

Features of the MT8941BP   are:(1)Provides T1 clock at 1.544 MHz locked to an 8 kHz reference clock (frame pulse); (2)Provides CEPT clock at 2.048 MHz and ST-BUS clock and timing signals locked to an internal or external 8 kHz reference clock; (3)Typical inherent output jitter (un?ltered)= 0.07 UI peak-to-peak; (4)Typical jitter attenuation at: 10 Hz=23 dB,100 Hz=43 dB, 5 to 40 kHz 64 dB; (5)Jitter-free "FREE-RUN" mode; (6)Uncommitted two-input NAND gate; (7)Low power CMOS technology.

The absolute maximum ratings of the MT8941BP   can be summarized as:(1)Supply Voltage VDD :-0.3~7.0 V; (2)Voltage on any pin VI :VSS-0.3 ~VDD+0.3 V; (3)Input/Output Diode Current I IK/OK: ±10 mA; (4)Output Source or Sink Current IO:±25 mA; (5)DC Supply or Ground Current IDD/ISS :±50 mA; (6)Storage Temperature TST:-55 ~125oC; (7)Package Power Dissipation Plastic DIP PD:1200 mW; (8)PLCC:600mW.

If you want to know more information such as the electrical characteristics of MT8941BP,please download the datasheet in www.seekdatasheet.com .