MT8941B

Features:

• Provides T1 clock at 1.544 MHz locked to an 8 kHz reference clock (frame pulse)
• Provides CEPT clock at 2.048 MHz and ST-BUS clock and timing signals locked to an internal or external 8 kHz refe-rence clock
• Typical inherent output jitter (unfiltered)= 0.07 UI peak-to-peak
• Typical jitter attenuation at: 10 Hz=23 dB,100 Hz=43 dB, 5 to 40 kHz 64 dB
• Jitter-free "FREE-RUN" mode
• Uncommitted two-input NAND gate
• Low power CMOS technology


Application

• Synchronization   and   timing   control   for T1 and CEPT digital trunk transmission links
• ST- BUS clock and frame pulse source


Pinout




Specifications

	Parameter	Symbol	Min	Max	Units
1	Supply Voltage	VDD	-0.3	7.0	V
2	Voltage on any pin	VI	VSS-0.5	VDD+0.5	V
3	Input/Output Diode Current	IIK/OK		±10	mA
4	Output Source or Sink Current	IO		±25	mA
5	DC Supply or Ground Current	IDD/ISS		±50	mA
6	Storage Temperature	TST	-65	150	°C
7	Package Power Dissipation Plastic DIP PLCC	PD PD		600 1200	mW mW

Description

The MT8941B is a dual digital phase-locked loop providing the timing and synchronization signals for the T1 or CEPT transmission links and the ST-BUS. The first PLL provides the T1 clock (1.544 MHz) synchronized to the input frame pulse at 8 kHz. The timing signals for the CEPT transmission link and the ST-BUS are provided by the second PLL lock-ed to an internal or an external 8 kHz frame pulse signal. The MT8941B offers improved jitter performance over the MT8940. The two devices also have some functional differences, which are listed in the section on "Differences bet-ween MT8941B and MT8940".