MT8940AE

The MT8940AE is a kind of dual digital phase-locked loop which provides the timing and synchronization signals for the T1 or CEPT transmission links and the ST-BUS. The first PLL provides the T1 clock (1.544 MHz),synchronized to the input frame pulse at 8 kHz. The timing signals for the CEPT transmission link and the ST-BUS are provided by the second PLL locked to an internal or an external 8 kHz frame pulse signal. The MT8940AE is fabricated in MITEL's ISO-CMOS technology. The typical applications of MT8940AE include: synchronization and timing control for T1 and CEPT digital trunk transmission links and ST- BUS clock and frame pulse source.

There are some features of MT8940AE as follows: (1)provides T1 clock at 1.544 MHz locked to input frame pulse; (2)sources CEPT (30+2) Digital Trunk/ST-BUS clock and timing signals locked to internal or external 8 kHz signal; (3)TTL compatible logic inputs and outputs; (4)uncommitted 2-input NAND gate; (5)single 5 volt power supply; (6)low power ISO-CMOS technology.

The following is about the absolute maximum ratings of MT8940AE (voltages are with respect to ground (VSS) unless otherwise stated): (1)supply voltage, VDD: -0.3 to 7.0 V; (2)voltage on any pin, VI: VSS-0.5 to VDD+0.5 V; (3)input/output diode current, IIK/OK: ±10 mA; (4)output source or sink current, IO: ±25 mA; (5)dc supply or ground current, IDD/ISS: ±50 mA; (6)storage temperature, TST: -65 to 150; (7)package power dissipation LCC, PD: 600 mW. Then is about the recommended operating conditions (voltages are with respect to ground (VSS) unless otherwise stated): (1)supply voltage, VDD: 4.75 V min, 5.0 V typ and 5.25 V max; (2)input HIGH voltage, VIH: 2.4 V min and VDD V max for 400 mV noise margin; (3)input LOW voltage, VIL: VSS V min and 0.4 V max for 400 mV noise margin; (4)operating temperature, TA: -40 min,  25 typ and 85 max.