MT54W4MH8B

• DLL circuitry for accurate output data placement
• Separate independent read and write data ports with concurrent transactions
• 100 percent bus utilization DDR READ and WRITE operation
• Fast clock to valid data times
• Full data coherency, providing most current data
• Two-tick burst counter for low DDR transaction size
• Double data rate operation on read and write ports
• Two input clocks (K and K#) for precise DDR timing at clock rising edges only
• Two output clocks (C and C#) for precise flight time and clock skew matching-clock and data delivered together to receiving device
• Single address bus
• Simple control logic for easy depth expansion
• Internally self-timed, registered writes
• +1.8V core and HSTL I/O
• Clock-stop capability
• 15mm x 17mm, 1mm pitch, 11 x 15 grid FBGA package
• User-programmable impedance output
• JTAG boundary scan

The Micron® QDR™II (Quad Data Rate™) synchronous, pipelined burst SRAM MT54W4MH8B employs high-speed, lowpower CMOS designs using an advanced 6T CMOS process.

The QDR architecture of MT54W4MH8B consists of two separate DDR (double data rate) ports to access the memory array.

The read port of MT54W4MH8B has dedicated data outputs to support READ operations. The write port has dedicated data inputs to support WRITE operations. This architecture eliminates the need for high-speed bus turnaround.

Access to each port of MT54W4MH8B is accomplished using a common address bus. Addresses for reads and writes are latched on rising edges of the K and K# input clocks, respectively.

Each address location of MT54W4MH8B is associated with two words that burst sequentially into or out of the device.Since data can be transferred into and out of the device on every rising edge of both clocks (K and K#, C and C#), memory bandwidth is maximized while system design is simplified by eliminating bus turnarounds.

Depth expansion of MT54W4MH8B  is accomplished with port selects for each port (read R#, write W#), which are received at K rising edge. Port selects permit independent port operation.

All synchronous inputs of MT54W4MH8B pass through registers controlled by the K or K# input clock rising edges. Active LOW byte writes (BWx#) permit byte or nibble write selection. Write data and byte writes are registered on the rising edges of both K and K#. The addressing within each burst of two is fixed and sequential, beginning with the lowest and ending with the highest address. All synchronous data outputs of MT54W4MH8B pass through output registers controlled by the rising edges of the output clocks (C and C# if provided, otherwise K and K#).

Four balls of MT54W4MH8B are used to implement JTAG test capabilities: test mode select (TMS), test data-in (TDI), test clock (TCK), and test data-out (TDO). JTAG circuitry is used to serially shift data to and from the SRAM. JTAG inputs use JEDEC-standard 1.8V I/O levels to shift data during this testing mode of operation.

The SRAM MT54W4MH8B operates from a +1.8V power supply, and all inputs and outputs are HSTL-compatible. The device is ideally suited for applications that benefit from a high-speed, fully-utilized DDR data bus.

Please refer to Micron's Web site (www.micron.com/ sramds) for the latest data sheet.