MT49H16M18

The Micron^® 288Mb reduced latency DRAM (RLDRAM^®) II MT49H16M18 is a high-speed memory device designed for high bandwidth communication data storage-telecommunications, networking, and cache applications, etc. The MT49H16M18's 8-bank architecture is optimized for high speed and achieves a peak bandwidth of 28.8 Gb/s, using a 36-bit interface and a maximum system clock of 400 MHz.

The double data rate (DDR) interface of MT49H16M18 transfers two 36-, 18-, or 9-bit wide data word per clock cycle at the I/O pins. Output data is referenced to the free-running output data clock.

Commands, addresses, and control signals are registered at every positive edge of the differential input clock, while input data is registered at both positive and negative edges of the input data clock(s).

Read and write accesses to the RLDRAM MT49H16M18 are burst-oriented. The burst length is programmable from 2, 4, or 8¹ by setting the mode register.

The MT49H16M18 is supplied with 2.5V and 1.8V for the core and 1.5V or 1.8V for the output drivers.

Bank-scheduled refresh of MT49H16M18 is supported with row address generated internally. A standard BGA 144-ball package is used to enable ultra high-speed data transfer rates and a simple upgrade path from former products.
Notes: 1. Burst of 8 on x18 and x9 devices only.