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MT48LC8M32B2

Features: • PC100 functionality• Fully synchronous; all signals registered on positive edge of system clock• Internal pipelined operation; column address can be changed every clock cycle• Internal banks for hiding row access/precharge• Programmable burst lengths: 1, 2...

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SeekIC No. : 004429865 Detail

MT48LC8M32B2: Features: • PC100 functionality• Fully synchronous; all signals registered on positive edge of system clock• Internal pipelined operation; column address can be changed every clock...

MT48LC8M32B2 Data Sheet

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Part Number:
MT48LC8M32B2
Supply Ability:
5000

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Product Details

Description



Features:

• PC100 functionality
• Fully synchronous; all signals registered on positive edge of system clock
• Internal pipelined operation; column address can be changed every clock cycle
• Internal banks for hiding row access/precharge
• Programmable burst lengths: 1, 2, 4, 8, or full page
• Auto Precharge, includes CONCURRENT AUTO PRECHARGE, and Auto Refresh Modes
• Self Refresh Mode
• 64ms, 4,096-cycle refresh (15.6µs/row)
• LVTTL-compatible inputs and outputs
• Single +3.3V ±0.3V power supply
• Supports CAS latency of 1, 2, and 3


Application

The 256Mb SDRAM is a high-speed CMOS, dynamic random-access memory containing 268,435,456-bits. It is internally configured as a quad-bank DRAM with a synchronous interface (all signals are registered on the positive edge of the clock signal, CLK). Each of the 67,108,864-bit banks is organized as 4,096 rows by 512 columns by 32 bits.

Read and write accesses to the SDRAM are burst oriented; accesses start at a selected location and con-tinue for a programmed number of locations in a pro-grammed sequence. Accesses begin with the registra-tion of an ACTIVE command, which is then followed by a READ or WRITE command. The address bits regis-tered coincident with the ACTIVE command are used to select the bank and row to be accessed (BA0, BA1 select the bank, A0A11 select the row). The address bits registered coincident with the READ or WRITE com-mand are used to select the starting column location for the burst access.


Pinout

Connection Diagram


Specifications

Voltage on VDD, VDDQ Supply Relative to VSS ........................ -1V to +4.6V
Voltage on Inputs, NC or I/O Pins Relative to VSS ................... -1V to +4.6V
Operating Temperature, TA ................................................. 0°C to +70°C
Storage Temperature (plastic) ....................................... -55°C to +150°C
Power Dissipation .................................................................................. 1W
Operating Temperature, TA (IT) ....................................... -40°C to +85°C


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