Features: Temperature Compensated Self Refresh (TCSR)
Fully synchronous; all signals registered on positive edge of system clock
Internal pipelined operation; column address can be changed every clock cycle
Internal banks for hiding row access/precharge
Programmable burst lengths: 1, 2, 4, 8, or full page
Auto Precharge, includes CONCURRENT AUTO PRECHARGE, and Auto Refresh Modes
Self Refresh Mode; standard and low power
64ms, 4,096-cycle refresh
LVTTL-compatible inputs and outputs
Low voltage power supply
Partial Array Self Refresh power-saving mode
Operating Temperature Range Industrial (-40 to +85)SpecificationsVoltage on VDD/VDDQ Supply
Relative to VSS(3.3V)............................... -1V to +4.6V
elative to VSS(2.5V) ............................. -0.5V to +3.6V
Voltage on Inputs, NC or I/O Pins
Relative to VSS(3.3V) ............................... -1V to +4.6V
Relative to VSS(2.5V)............................. -0.5V to +3.6V
Operating Temperature,
TA(Industrial) ......................................... -40 to +85
Storage Temperature (plastic)...............-55 to +150
Power Dissipation .....................................................1WDescriptionThe Micron®128Mb SDRAM MT48LC8M16LFFF is a high-speed CMOS,dynamic random-access memory containing 134,217,728 bits. It is internally configured as a quad-bank DRAM with a synchronous interface (all signals are registered on the positive edge of the clock signal, CLK). Each of the x16's 33,554,432-bit banks is organized as 4,096 rows by 512 columns by 16 bits. Each of the x32's 33,554,432-bit banks is organized as 4,096 rows by 256 columns by 32 bits.
Read and write accesses to the SDRAM MT48LC8M16LFFF are burst ori-ented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of an AC-TIVE command, which is then followed by a READ or WRITE command. The address bits of MT48LC8M16LFFF registered coinci-dent with the ACTIVE command are used to select the bank and row to be accessed (BA0, BA1 select the bank; A0-A11 select the row). The address bits registered coin-cident with the READ or WRITE command are used to select the starting column location for the burst access.
The SDRAM MT48LC8M16LFFF provides for programmable READ or WRITE burst lengths of 1, 2, 4, or 8 locations, or the full page, with a burst terminate option. An auto precharge function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst se-quence.
The 128Mb SDRAM MT48LC8M16LFFF uses an internal pipelined architecture to achieve high-speed operation. This architecture is compatible with the 2n rule of prefetch architectures, but it also allows the column address to be changed on every clock cycle to achieve a high-speed,fully random access. Precharging one bank of MT48LC8M16LFFF while access-ing one of the other three banks will hide the precharge cycles and provide seamless high-speed, random-access operation.
The 128Mb SDRAM MT48LC8M16LFFF is designed to operate in 3.3V or 2.5V, low-power memory systems. An auto refresh mode is provided, along with a power-saving, power-down mode. All inputs and outputs are LVTTL-compatible.
SDRAMs MT48LC8M16LFFF offer substantial advances in DRAM operat-ing performance, including the ability to synchronously burst data at a high data rate with automatic column-address generation, the ability to interleave between in-ternal banks in order to hide precharge time and the capability to randomly change column addresses on each clock cycle during a burst access.
MT48LC8M16LFFF Data Sheet
