MT48LC32M16A2

Features: • PC100- and PC133-compliant• Fully synchronous; all signals registered on positive edge of system clock• Internal pipelined operation; column address can be changed every clock cycle• Internal banks for hiding row access/precharge• Programmable burst length...

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MT48LC32M16A2 Picture
SeekIC No. : 004429836 Detail

MT48LC32M16A2: Features: • PC100- and PC133-compliant• Fully synchronous; all signals registered on positive edge of system clock• Internal pipelined operation; column address can be changed ever...

floor Price/Ceiling Price

Part Number:
MT48LC32M16A2
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2024/11/23

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Product Details

Description



Features:

• PC100- and PC133-compliant
• Fully synchronous; all signals registered on positive edge of system clock
• Internal pipelined operation; column address can be changed every clock cycle
• Internal banks for hiding row access/precharge
• Programmable burst lengths: 1, 2, 4, 8, or full page
• Auto Precharge, includes CONCURRENT AUTO PRECHARGE, and Auto Refresh Modes
• Self Refresh Mode
• 64ms, 8,192-cycle refresh
• LVTTL-compatible inputs and outputs
• Single +3.3V ±0.3V power supply



Pinout

  Connection Diagram


Specifications

Voltage on VDD, VDDQ Supply
Relative to VSS ....................................... -1V to +4.6V
Voltage on Inputs, NC or I/O Pins
Relative to VSS ....................................... -1V to +4.6V
Operating Temperature,
TA (Commercial) ..................................0°C to +70°C
Storage Temperature (plastic) ...... -55°C to +150°C
Power Dissipation ................................................. 1W



Description

The 512Mb SDRAM MT48LC32M16A2 is a high-speed CMOS, dynamic random-access memory containing 536,870,912 bits. It is internally configured as a quad-bank DRAM with a syn- chronous interface (all signals are registered on the posi- tive edge of the clock signal, CLK). Each of the x4's 134,217,728-bit banks is organized as 8,192 rows by 4,096 columns by 4 bits. Each of the x8's 134,217,728-bit banks of MT48LC32M16A2 is organized as 8,192 rows by 2,048 columns by 8 bits. Each of the x16's 134,217,728-bit banks is organized as 8,192 rows by 1,024 columns by 16 bits.

Read and write accesses to the SDRAM MT48LC32M16A2 are burst ori-ented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of an AC-TIVE command, which is then followed by a READ or WRITE command. The address bits of MT48LC32M16A2 registered coincident with the ACTIVE command are used to select the bank and row to be accessed (BA0, BA1 select the bank; A0-A12 select the row). The address bits registered coincident with the READ orWRITE command are used to select the starting column location for the burst access.




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