MT48LC2M8A1S-1

The Micron 16Mb SDRAM MT48LC2M8A1S-1 is a high-speed CMOS, dynamic random-access memory containing 16,777,216 bits. It is internally configured as a dual memory array (the 4 Meg x 4 is a dual 2 Meg x 4, and the 2 Meg x 8 is a dual 1 Meg x 8) with a synchronous interface (all signals are registered on the positive edge of the clock signal, CLK). Each of the two internal banks of MT48LC2M8A1S-1 is organized with 2,048 rows and either 1,024 columns by 4 bits (4 Meg x 4) or 512 columns by 8 bits (2 Meg x 8).

Read and write accesses to the SDRAM MT48LC2M8A1S-1 are burst ori- ented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of an AC- TIVE command, which is then followed by a READ or WRITE command. The address bits of MT48LC2M8A1S-1 registered coinci- dent with the ACTIVE command are used to select the bank and row to be accessed (BA selects the bank, A0-A10 select the row). The address bits registered coincident with the READ or WRITE command are used to select the starting column location for the burst access.