MT48LC1M16A1TGS

The 16Mb SDRAM MT48LC1M16A1TGS is a high-speed CMOS, dynamic random-access memory containing 16,777,216 bits. It is internally configured as a dual 512K x 16 DRAM witha synchronous interface (all signals are registered on the positive edge of the clock signal, CLK). Each of the 512K x 16-bit banks of MT48LC1M16A1TGS is organized as 2,048 rows by 256 columns by 16 bits. Read and write accesses to the SDRAM are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of an ACTIVE command, which is then followed by a READ or WRITE command. The address bits of MT48LC1M16A1TGS registered coincident with the ACTIVE command are used to select the bank and row to be accessed (BA selects the bank, A0-A10 select the row).

The address bits of MT48LC1M16A1TGS registered coincident with the READ or WRITE command are used to select the starting col- umn location for the burst access.