Features: • Endur-IC™ technology
• Fully synchronous; all signals registered on positive edge of system clock
• VDD = 1.71.95V; VDDQ = 1.71.95V
• Internal, pipelined operation; column address can be changed every clock cycle
• Four internal banks for concurrent operation
• Programmable burst lengths: 1, 2, 4, 8, and continuous1
• Auto precharge, includes concurrent auto precharge
• Auto refresh and self refresh modes
• LVTTL-compatible inputs and outputs
• On-chip temperature sensor to control refresh rate
• Partial-array self refresh (PASR)
• Deep power-down (DPD)
• Selectable output drive (DS)Specifications
| Voltage/Temperature |
Min |
Max |
Units |
Voltage on VDD/VDDQ supply relative to VSS
Voltage on inputs, NC or I/O balls relative to VSS
Storage temperature plastic |
0.3
0.3
55 |
+2.7
+2.7
+150 |
V
°C |
DescriptionThe Micron® 512Mb Mobile SDRAM MT48H16M32LG is a high-speed CMOS, dynamic random-access memory containing 536,870,912-bits. It is internally configured as a quad-bank DRAM with a synchronous interface (all signals are registered on the positive edge of the clock signal, CLK). Each of the x16's 134,217,728-bit banks is organized as 8,192 rows by 1K columns by 16 bits. Each of the x32's 134,217,728-bit banks of MT48H16M32LG is organized as 8,192 rows by 512 columns by 32 bits. In a reduced page-size option, each of the x32's 134,217,728-bit banks is organized as 16,384 rows by 256 columns x32 bits.
Read and write accesses to the SDRAM MT48H16M32LG are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of an ACTIVE command, which is then followed by a READ or WRITE command. The address bits of MT48H16M32LG registered coincident with the ACTIVE command are used to select the bank and row to be accessed (BA0, BA1 select the bank; A0A12 select the row). The address bits registered coincident with the READ or WRITE command are used to select the starting column location for the burst access.
The SDRAM MT48H16M32LG provides for programmable read or write burst lengths (BL) of 1, 2, 4, or 8 locations with a read burst terminate option. An auto precharge function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst sequence.
The 512Mb SDRAM MT48H16M32LG uses an internal pipelined architecture to achieve high-speed operation.
This architecture of MT48H16M32LG is compatible with the 2n rule of prefetch architectures, but it also allows the column address to be changed on every clock cycle to achieve a highspeed, fully random access. Precharging one bank while accessing one of the other three banks will hide the PRECHARGE cycles and provide seamless high-speed, randomaccess operation.
MT48H16M32LG Data Sheet
