Features: • Temperature Compensated Self Refresh (TCSR)
• Fully synchronous; all signals registered on positive edge of system clock
• Internal pipelined operation; column address can be changed every clock cycle
• Internal banks for hiding row access/precharge
• Programmable burst lengths: 1, 2, 4, 8, or full page
• Auto Precharge, includes CONCURRENT AUTO PRECHARGE and Auto Refresh Modes
• Self Refresh Mode
• 64ms, 8,192-cycle refresh
• LVTTL-compatible inputs and outputs
• Low voltage power supply
• Deep Power Down
• Partial Array Self Refresh power-saving mode
• Industrial operating temperature (-40oC to +85oC)Pinout
SpecificationsVoltage on VDD/VDDQ Supply
Relative to VSS(2.5V) ......................... -0.5V to +3.6V
Relative to VSS(1.8V) ....................... -0.35V to +2.8V
Voltage on Inputs, NC or I/O Pins
Relative to VSS(1.8V) ...................... -0.35V to +2.8V
Operating Temperature,
TA (industrial; IT parts) ................... -40°C to +85°C
Storage Temperature (plastic) ......... -55°C to +150°C
Power Dissipation .................................................... 1W
*Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to
the device. This is a stress rating only, and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.DescriptionThe 256Mb SDRAM MT48H16M16LFFG is a high-speed CMOS, dynamic random-access memory containing 268,435,456 bits. It is internally configured as a quadbank DRAM with a synchronous interface (all signals are registered on the positive edge of the clock signal, CLK). Each of the x16's 67,108,864-bit banks is organized as 8,192 rows by 512 columns by 16 bits.
Read and write accesses to the SDRAM MT48H16M16LFFG are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of an ACTIVE command, which is then followed by a READ or WRITE command. The address bits of MT48H16M16LFFG registered coincident with the ACTIVE command are used to select the bank and row to be accessed (BA0, BA1 select the bank; A0A12 select the row). The address bits registered coincident with the READ or WRITE command are used to select the starting column location for the burst access.
The SDRAM MT48H16M16LFFG provides for programmable READ or WRITE burst lengths of 1, 2, 4, or 8 locations, or the full page, with a burst terminate option. An auto precharge function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst sequence.
The 256Mb SDRAM MT48H16M16LFFG uses an internal pipelined architecture to achieve high-speed operation. This architecture is compatible with the 2n rule of prefetch architectures, but it also allows the column address to be changed on every clock cycle to achieve a highspeed, fully random access. Precharging one bank while accessing one of the other three banks will hide the precharge cycles and provide seamless, highspeed, random-access operation.
The 256Mb SDRAM MT48H16M16LFFG is designed to operate in 2.5V and 1.8V memory systems. An auto refresh mode is provided, along with a power-saving, power-down mode. All inputs and outputs are LVTTL-compatible.
SDRAMs MT48H16M16LFFG offer substantial advances in DRAM operating performance, including the ability to synchronously burst data at a high data rate with automatic column-address generation, the ability to interleave between internal banks to hide precharge time and the capability to randomly change column addresses on each clock cycle during a burst access.
MT48H16M16LFFG Data Sheet
