MT47H128M4BT-5E

The MT47H128M4BT-5E is a kind of 32 Meg*4*4 banks DDR2 SDRAM (Synchronous Dynamic Random Access Memory). It uses a double data rate architecture to achieve high-speed operation. The MT47H128M4BT-5E provides for programmable READ or WRITE burst lengths of four or eight locations. Besides, it supports interrupting a burst READ of eight with another READ or a burst WRITE of eight with another WRITE. All inputs of MT47H128M4BT-5E are compatible with the JEDEC standard for SSTL_18. All full drive-strength outputs are SSTL_18-compatible.

There are some features of MT47H128M4BT-5E as follows. (1) differential data strobe (DQS, DQS#) option; (2) 4n-bit prefetch architecture; (3) duplicate output strobe (RDQS) option for x8; (4) DLL to align DQ and DQS transitions with CK; (5) 4 internal banks for concurrent operation; (6) programmable CAS latency (CL); (7) posted CAS additive latency (AL); (8) selectable burst lengths (BL): 4 or 8; (9) adjustable data-output drive strength; (8) 64ms, 8,192-cycle refresh; (9) on-die termination (ODT); (10) industrial temperature (IT) option; (11) automotive temperature (AT) option; (12) supports JEDEC clock jitter specification.

The following is about the absolute maximum ratings of MT47H128M4BT-5E. (1): VDD (supply voltage relative to VSS) is from -1.0 to 2.3 V; (2): VDDQ (supply voltage relative to VSSQ) is from -0.5 to +2.3 V; (3): VDDL (supply voltage relative to VSSL) is from -0.5 to +2.3 V; (4):VIN, VOUT (voltage on any ball relative to VSS) is from -0.5 to +2.3 V; (5): II (input leakage current; any input 0 V VIN VDD; all other balls not under test=0 V) is from -5 to +5A; (6): IOZ (output leakage current; 0 V VOUT VDDQ; DQ and ODT disabled) is from -5 to +5A; (7) IREF (VREF leakage current; VREF=Valid VREF level) is from -2 to +2A.