MT46V8M16TG-75L

The MT46V8M16TG-75L is a high-speed CMOS, dynamic random-access memory that operates at a frequency of 167 MHz (tCK=6ns) with a peak data transfer rate of 333Mb/s/p. DDR333 continues to use the JEDEC standard SSTL_2 interface and the 2n-prefetch architecture.

The features of the MT46V8M16TG-75L are: (1)167 MHz Clock, 333 Mb/s/p data rate; (2)VDD = +2.5V ±0.2V, VDDQ = +2.5V ±0.2V; (3)Bidirectional data strobe (DQS) transmitted/received with data, i.e., source-synchronous data capture; (4)Internal, pipelined double-data-rate (DDR)architecture; two data accesses per clock cycle; (5)Differential clock inputs (CK and CK#); (6)Commands entered on each positive CK edge; (7)DQS edge-aligned with data for READs; centeraligned with data for WRITEs; (8)DLL to align DQ and DQS transitions with CK; (9)Four internal banks for concurrent operation; (10)Data mask (DM) for masking write data; (11)Programmable burst lengths: 2, 4, or 8; (12)Concurrent Auto Precharge option supported; (13)Auto Refresh and Self Refresh Modes; (14)FBGA package available; (15)2.5V I/O (SSTL_2 compatible); (16)tRAS lockout (tRAP = tRCD).