MT46V32M4

• 167 MHz Clock, 333 Mb/s/p data rate
• VDD = +2.5V ±0.2V, VDDQ = +2.5V ±0.2V
• Bidirectional data strobe (DQS) transmitted/received with data, i.e., source-synchronous data capture (x16 has two - one per byte)
• Internal, pipelined double-data-rate (DDR)architecture; two data accesses per clock cycle
• Differential clock inputs (CK and CK#)
• Commands entered on each positive CK edge
• DQS edge-aligned with data for READs; centeraligned with data for WRITEs
• DLL to align DQ and DQS transitions with CK
• Four internal banks for concurrent operation
• Data mask (DM) for masking write data (x16 has two - one per byte)
• Programmable burst lengths: 2, 4, or 8
• Concurrent Auto Precharge option supported
• Auto Refresh and Self Refresh Modes
• FBGA package available
• 2.5V I/O (SSTL_2 compatible)
• tRAS lockout (tRAP = tRCD)
• Backwards compatible with DDR200 and DDR266

The DDR333 SDRAM MT46V32M4 is a high-speed CMOS, dynamic random-access memory that operates at a frequency of 167 MHz (tCK=6ns) with a peak data transfer rate of 333Mb/s/p. DDR333 continues to use the JEDEC standard SSTL_2 interface and the 2n-prefetch architecture.

The standard DDR200/DDR266 data sheets of MT46V32M4 also pertain to the DDR333 device and should be referenced for a complete description of DDR SDRAM functionality and operating modes. However, to meet the faster DDR333 operating frequencies, some of the AC timing parameters are slightly tighter. This addendum data sheet will concentrate on the key differences required to support the enhanced speeds.

In addition to the standard 66-pin TSOP package,a 60-ball FBGA package is utilized for DDR333 MT46V32M4. This JEDEC-defined package promotes better package parasitic parameters and a smaller footprint.