MT46V2M32LG

• Bidirectional data strobe (DQS) transmitted/ received with data, i.e., source-synchronous data capture
• Internal, pipelined double-data-rate (DDR) architecture; two data accesses per clock cycle
• Reduced output drive option
• Differential clock inputs (CK and CK#)
• Commands entered on each positive CK edge
• DQS edge-aligned with data for READs; centeraligned with data for WRITEs
• DLL to align DQ and DQS transitions with CK
• Four internal banks for concurrent operation
• Data mask (DM) for masking write data
• Programmable burst lengths: 2, 4, 8, or full page
• 32ms, 4,096-cycle auto refresh (7.8s/cycle)
• Auto precharge option
• Auto Refresh and Self Refresh Modes
• Programmable I/O (SSTL_2 compatible) reduced and impedance matched

Voltage on V_DD Supply
Relative to V_SS ......................................... -1V to +3.6V
Voltage on V_DDQ Supply
Relative to V_SS ......................................... -1V to +3.6V
Voltage on V_REF and Inputs
Relative to V_SS ......................................... -1V to +3.6V
Voltage on I/O Pins
Relative to V_SS ........................... -0.5V to V_DDQ +0.5V
Operating Temperature, T_A (ambient).. 0°C to +70°C
Storage Temperature (plastic) .........-55°C to +150°C
Power Dissipation ................................................... 1W
Short Circuit Output Current ............................... 50mA

*Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

The 64Mb (x32) DDR SDRAM MT46V2M32LG is a high-speed CMOS, dynamic random-access memory containing 67,108,864 bits. It is internally configured as a quadbank DRAM.

The 64Mb DDR SDRAM MT46V2M32LG uses a double data rate architecture to achieve high-speed operation. The double data rate architecture is essentially a 2nprefetch architecture with an interface designed to transfer two data words per clock cycle at the I/O pins.A single read or write access for the 64Mb DDR SDRAM MT46V2M32LG effectively consists of a single 2n-bit wide, one-clockcycle data transfer at the internal DRAM core and two corresponding n-bit wide, one-half-clock-cycle data transfers at the I/O pins.

A bidirectional data strobe (DQS) of MT46V2M32LG is transmitted externally, along with data, for use in data capture at the receiver. DQS is a strobe transmitted by the DDR SDRAM during READs and by the memory controller during WRITEs. DQS is edge-aligned with data for READs and center-aligned with data for WRITEs.

The 64Mb DDR SDRAM MT46V2M32LG operates from a differential clock (CK and CK#); the crossing of CK going HIGH and CK# going LOW will be referred to as the positive edge of CK. Commands (address and control signals) are registered at every positive edge of CK. Input data is registered on both edges of DQS, and output data is referenced to both edges of DQS, as well as to both edges of CK.

Read and write accesses to the DDR SDRAM MT46V2M32LG are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of an ACTIVE command, which is then followed by a READ or WRITE command. The address bits registered coincident with the ACTIVE command are used to select the bank and row to be accessed. The address bits registered coincident with the READ or WRITE command are used to select the bank and the starting column location for the burst access.

The DDR SDRAM MT46V2M32LG provides for programmable READ or WRITE burst lengths of 2, 4, 8, or full page locations. An auto precharge function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst access.

As with standard SDR SDRAMs MT46V2M32LG, the pipelined, multibank architecture of DDR SDRAMs allows for concurrent operation, thereby providing high effective bandwidth by hiding row precharge and activation time.

An auto refresh mode of MT46V2M32LG is provided, along with a power-saving power-down mode. All inputs are compatible with the JEDEC Standard for SSTL_2. All outputs are SSTL_2.

NOTE: 1. The functionality and the timing specifications discussed in this data sheet are for the DLL-enabled mode of operation.

2. Throughout the data sheet, the various figures and text refer to DQs as "DQ." The DQ term is to be interpreted as any and all DQ collectively, unless specifically stated otherwise.