MT46V16M8

• 200 MHz Clock, 400 Mb/s/p data rate
• V_DD = +2.65V ±0.10V
• V_DDQ = +2.65V ±0.10V
• Bidirectional data strobe (DQS) transmitted/
   received with data, i.e., source-synchronous data
   capture
• Internal, pipelined double-data-rate (DDR)
architecture; two data accesses per clock cycle
• Differential clock inputs (CK and CK#)
• Commands entered on each positive CK edge
• DQS edge-aligned with data for READs; centeraligned
   with data for WRITEs
• DLL to align DQ and DQS transitions with CK
• Four internal banks for concurrent operation
• Data mask (DM) for masking write data
• Programmable burst lengths: 2, 4, or 8
• Concurrent Auto Precharge option supported
• Auto Refresh and Self Refresh Modes
• ^tRAS lockout (^tRAP = ^tRCD)

V_DD Supply Voltage Relative to V_SS ....... .-1V to +3.6V
V_DDQ Supply Voltage Relative to V_SS .......-1V to +3.6V
V_REF and Inputs Voltage Relative to V_SS . -1V to +3.6V
I/O Pins Voltage Relative to VSS . -0.5V to V_DDQ +0.5V
Operating Temperature, T_A (ambient) ..0°C to +50°C
Storage Temperature (plastic) ........-55°C to +150°C
Power Dissipation .................................................. 1W
Short Circuit Output Current ...............................50mA

The DDR400 SDRAM MT46V16M8 is a high-speed CMOS, dynamic random-access memory that operates at a frequency of 200 MHz (^tCK=5ns) with a peak data transfer rate of 400Mb/s. DDR400 continues to use the JEDEC standard SSTL_2 interface and the 2n-prefetch architecture.

The standard DDR200/DDR266 data sheets also pertain to the DDR400 device and should be referenced for a complete description of DDR SDRAM functionality and operating modes. However, to meet the faster DDR400 operating frequencies, some of the AC timing parameters, DC levels and operating temperatures are slightly tighter. This addendum data sheet will concentrate on the key differences required to support the enhanced speeds.

The Micron 128Mb data sheet of MT46V16M8 provides full specifications and functionality unless specified herein.