Features: • VDD = VDDQ = +1.5V ±0.075V
• 1.5V center-terminated push/pull I/O
• Differential bidirectional data strobe
• 8n-bit prefetch architecture
• Differential clock inputs (CK, CK#)
• 8 internal banks
• Nominal and dynamic on-die termination (ODT) for data, strobe, and mask signals
• CAS (READ) latency (CL): 5, 6, 7, 8, 9, 10, or 11
• POSTED CAS ADDITIVE latency (AL): 0, CL - 1, CL - 2
• CAS (WRITE) latency (CWL): 5, 6, 7, 8, based on tCK
• Fixed burst length (BL) of 8 and burst chop (BC) of 4 (via the mode register set [MRS])
• Selectable BC4 or BL8 on-the-fly (OTF)
• Self refresh mode
• TC of 0 to 95
64ms, 8,192 cycle refresh at 0 to 85
32ms at 85 to 95
• Clock frequency range of 300800 MHz
• Self refresh temperature (SRT)
• Automatic self refresh (ASR)
• Write leveling
• Multipurpose register
• Output driver calibrationSpecifications
| Symbol |
Parameter |
Min. |
Max. |
Unit |
Note |
| VDD |
VDD supply voltage relative to VSS |
0.4 |
1.975 |
V |
1 |
| VDDQ |
VDD supply voltage relative to VSSQ |
0.4 |
1.975 |
V |
|
| VIN, VOUT |
Voltage on any pin relative to VSS |
0.4 |
1.975 |
V |
|
| TC |
Operating case temperature |
0 |
95 |
|
2,3 |
| TSTG |
Storage Temperature |
-55 |
150 |
|
|
Notes: 1. VDD and VDDQ must be within 300mV of each other at all times, and VREF must not be greater than 0.6 * VDDQ. When VDD and VDDQ are less than 500mV, VREF may be 300mV.
2. MAX operating case temperature. TC is measured in the center of the package (see Figure 13 on page 28).
3. Device functionality is not guaranteed if the DRAM device exceeds the maximum TC during operation.
DescriptionThe DDR3 SDRAM MT41J256M4 uses a double data rate architecture to achieve high-speed operation.
The double data rate architecture of MT41J256M4 is an 8n-prefetch architecture with an interface designed to transfer two data words per clock cycle at the I/O pins. A single read or write access for the DDR3 SDRAM consists of a single 8n-bit-wide, one-clock-cycle data transfer at the internal DRAM core and eight corresponding n-bit-wide, one-half-clockcycle data transfers at the I/O pins.
The differential data strobe of MT41J256M4 (DQS, DQS#) is transmitted externally, along with data, for use in data capture at the DDR3 SDRAM input receiver. DQS is center-aligned with data for WRITEs. The read data is transmitted by the DDR3 SDRAM and edge-aligned to the data strobes.
The DDR3 SDRAM MT41J256M4 operates from a differential clock (CK and CK#). The crossing of CK going HIGH and CK# going LOW is referred to as the positive edge of CK. Control,command, and address signals are registered at every positive edge of CK. Input data is registered on the first rising edge of DQS after the WRITE preamble, and output data of MT41J256M4 is referenced on the first rising edge of DQS after the READ preamble.
Read and write accesses to the DDR3 SDRAM are burst-oriented. Accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of an ACTIVATE command, which is then followed by a READ or WRITE command. The address bits of MT41J256M4 registered coincident with the ACTIVATE command are used to select the bank and row to be accessed. The address bits registered coincident with the READ or WRITE commands are used to select the bank and the starting column location for the burst access.
DDR3 SDRAM MT41J256M4 use READ and WRITE BL8 and BC4. An auto precharge function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst access.
As with standard DDR SDRAM MT41J256M4, the pipelined, multibank architecture of DDR3 SDRAM allows for concurrent operation, thereby providing high bandwidth by hiding row precharge and activation time.
A self refresh mode of MT41J256M4 is provided, along with a power-saving, power-down mode.
MT41J256M4 Data Sheet
