MT32LD3264A X

The Micron^(R) MT8LD864A X, MT16LD1664A X and MT32LD3264A X are randomly accessed 64MB,128MB and 256MB memories organized in a x64 con-figuration. They are specially processed to operate from 3V to 3.6V for low-voltage memory systems. During READ or WRITE cycles, each bit is uniquely addressed through the 22/23 address bits, which are entered 12 bits (A0-A11) at RAS# time and 11/12 bits (A0-A11) at CAS# time.

READ and WRITE cycles of MT32LD3264A X are selected with the WE# input. A logic HIGH on WE# dictates read mode, while a logic LOW on WE# dictates write mode. During a WRITE cycle, data-in (D) is latched by the falling edge of WE# or CAS#, whichever occurs last. An EARLY WRITE occurs when WE# is taken LOW prior to CAS# falling. A LATE WRITE or READ-MODIFY-WRITE oc-curs when WE# falls after CAS# was taken LOW. During EARLY WRITE cycles, the data-outputs (Q) of MT32LD3264A X will remain High-Z regardless of the state of OE#. During LATE WRITE or READ-MODIFY-WRITE cycles, OE# must be taken HIGH to disable the data-outputs prior to applying input data. If a LATE WRITE or READ- MODIFY-WRITE is attempted while keeping OE# LOW,no WRITE will occur, and the data-outputs will drive read data from the accessed location.