MT28F004B5-1

• Seven erase blocks:
   16KB/8K-word boot block (protected)
   Two 8KB/4K-word parameter blocks
   Four main memory blocks
• Smart 5 technology (B5):
   5V ±10% V_CC
   5V ±10% V_PP application/production
   programming1
• Advanced 0.18m CMOS floating-gate process
• Compatible with 0.3m Smart 5 device
• Address access time: 80ns
• 100,000 ERASE cycles
• Industry-standard pinouts
• Inputs and outputs are fully TTL-compatible
• Automated write and erase algorithm
• Two-cycle WRITE/ERASE sequence
• Byte- or word-wide READ and WRITE
   (MT28F400B5, 256K x 16/512K x 8)
• Byte-wide READ and WRITE only
   (MT28F004B5, 512K x 8)
• TSOP and SOP packaging options

The MT28F004B5-1 are nonvolatile, electrically block-erasable (Flash), programmable, read-only memories containing 4,194,304 bits organized as 262,144 words (16 bits) or 524,288 bytes (8 bits). Writing or erasing the device is done with a 5V V_PP voltage, while all operations are performed with a 5V V_CC. Due to process technology advances, 5V V_PP is optimal for application and production programming. These MT28F004B5-1 are fabricated with Micron's advanced 0.18m CMOS floating-gate process.

The MT28F004B5-1 are organized into seven separately erasable blocks. To ensure that critical firmware is protected from accidental erasure or overwrite, the devices feature a hardware-protected boot block. Writing or erasing the boot block requires either applying a super-voltage to the RP# pin or driving WP# HIGH in addition to executing the normal write or erase sequences. This block of MT28F004B5-1 may be used to store code implemented in low-level system recovery. The remaining blocks vary in density and are written and erased with no additional security measures.