Features: • Flexible dual-bank architecture• Support for true concurrent operations with no latency: Read bank b during program bank a and vice versa Read bank b during erase bank a and vice versa• Organization: 4,096K x 16 (Flash)512K x 16 (SRAM)• Basic configuration: Flas...
MT28C6428P18: Features: • Flexible dual-bank architecture• Support for true concurrent operations with no latency: Read bank b during program bank a and vice versa Read bank b during erase bank a and ...
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Features: • Stacked die Combo package Includes two 64Mb Flash devices Choice of either one 3...
Features: • Stacked die Combo package Includes two 64Mb Flash devices Choice of either one 3...
The MT28C6428P20 and MT28C6428P18 combination Flash and SRAM memory devices provide a compact, low-power solution for systems where PCB real estate is at a premium. The dual-bank Flash devices are high-performance, high-density, nonvolatile memory with a revolutionary architecture that can significantly improve system performance.
This new architecture of MT28C6428P18 features:
• A two-memory-bank configuration supporting
dual-bank operation;
• A high-performance bus interface providing a fast
page data transfer; and
• A conventional asynchronous bus interface.
The MT28C6428P18 also provide soft protection for blocks by configuring soft protection registers with dedicated command sequences. For security purposes, dual 64- bit chip protection registers are provided.
The embedded WORD WRITE and BLOCK ERASE functions of MT28C6428P18 are fully automated by an on-chip write state machine (WSM). The WSM simplifies these operations and relieves the system processor of secondary tasks. An on-chip status register, one for each bank, can be used to monitor the WSM status to determine the progress of a PROGRAM/ERASE command.
The erase/program suspend functionality of MT28C6428P18 allows compatibility with existing EEPROM emulation software packages.
The MT28C6428P18 take advantage of a dedicated power source for the Flash memory (F_VCC) and a dedicated power source for the SRAM (S_VCC), both at 1.70V2.20V for optimized power consumption and improved noise immunity. A dedicated I/O power supply (VCCQ) is provided with an extended range (1.70V2.20V), to allow a direct interface to most common logic controllers and to ensure improved noise immunity. The separate S_VCC pin for the SRAM provides data retention capability when required. The data retention S_VCC is specified as low as 1.0V. The MT28C6428P20 and MT28C6428P18 devices support two F_VPP voltage ranges, an in-circuit voltage of 0.9V2.2V and a production compatibility voltage of 12V ±5%. The 12V ±5% F_VPP2 is supported for a maximum of 100 cycles and 10 cumulative hours.
The MT28C6428P20 and MT28C6428P18 contain an asynchronous 8Mb SRAM organized as 512K-words by 16 bits. The devices are fabricated using an advanced CMOS process and high-speed/ultra-lowpower circuit technology, and then are packaged in a67-ball FBGA package with 0.80mm pitch.