MT28C3224P20

Voltage to Any Ball Except V_CC and V_PP
with Respect to V_SS ............................ -0.5V to +2.45V
V_PP Voltage (for BLOCK ERASE and PROGRAM
with Respect to V_SS) ....................... -0.5V to +13.5V**
V_CC and V_CCQ Supply Voltage
with Respect to V_SS ............................ -0.3V to +2.45V
Output Short Circuit Current ..............................100mA
Operating Temperature Range .............. -40 to +85
Storage Temperature Range ............... -55 to +125
Soldering Cycle ........................................ 260 for 10s

The MT28C3224P20 and MT28C3224P18 combination Flash and SRAM memory devices provide a compact, low-power solution for systems where PCB real estate is at a premium. The dual-bank Flash devices are high-performance, high-density, nonvolatile memory with a revolutionary architecture that can significantly improve system performance.

This new architecture of MT28C3224P20 features:

• A two-memory-bank configuration supporting
  dual-bank operation;

• A high-performance bus interface providing a fast
  page data transfer; and

• A conventional asynchronous bus interface.

The MT28C3224P20 also provide soft protection for blocks by configuring soft protection registers with dedicated command sequences. For security purposes, dual 64- bit chip protection registers are provided.

The embedded WORD WRITE and BLOCK ERASE functions of MT28C3224P20 are fully automated by an on-chip write state machine (WSM). The WSM simplifies these operations and relieves the system processor of secondary tasks. An on-chip status register, one for each bank, can be used to monitor the WSM status to determine the progress of a PROGRAM/ERASE command.

The erase/program suspend functionality of MT28C3224P20 allows compatibility with existing EEPROM emulation software packages.

The MT28C3224P20 take advantage of a dedicated power source for the Flash memory (F_V_CC) and a dedicated power source for the SRAM memory (S_V_CC), both at 1.70V2.20V for optimized power consumption and improved noise immunity. A dedicated I/O power supply (V_CCQ) is provided with an extended range (1.70V 2.20V), to allow a direct interface to most common logic controllers and to ensure improved noise immunity.

The separate S_V_CC pin for the SRAM provides data retention capability when required. The data retention S_V_CC is specified as low as 1.0V. The MT28C3224P20 and MT28C3224P18 devices support two V_PP voltage ranges, an in-circuit voltage of 0.9V 2.2V and a production compatibility voltage of 12V ±5%. The 12V ±5% V_PP2 is supported for a maximum of 100 cycles and 10 cumulative hours.

The MT28C3224P20 and MT28C3224P18 devices contain an asynchronous 4Mb SRAM organized as 256Kwords by 16 bits. These devices are fabricated using an advanced CMOS process and high-speed/ultra-lowpower circuit technology.

The MT28C3224P20 are packaged in a 66-ball FBGA package with 0.80mm pitch.