MT28C3212P2NFL

• Flexible dual-bank architecture
• Support for true concurrent operations with no
   latency:
    Read bank b during program bank a and vice versa
    Read bank b during erase bank a and vice versa
• Organization: 2,048K x 16 (Flash)
    128K x 16 (SRAM)
• Basic configuration:
   Flash
    Bank a (4Mb Flash for data storage)
    Eight 4K-word parameter blocks
    Seven 32K-word blocks
   Bank b (28Mb Flash for program storage)
    Fifty-six 32K-word main blocks
   SRAM
   2Mb SRAM for data storage
    128K-words
• F_V_CC, V_CCQ, F_VPP, S_V_CC voltages1
   1.65V (MIN)/1.95V (MAX) F_V_CC read voltage or
    1.80V (MIN)/2.20V (MAX) F_V_CC read voltage
   1.65V (MIN)/1.95V (MAX) S_V_CC read voltage or
    1.80V (MIN)/2.20V (MAX) S_V_CC read voltage
   1.65V (MIN)/1.95V (MAX) V_CCQ or
    1.80V (MIN)/2.20V (MAX) V_CCQ
   1.80V (TYP) F_V_PP (in-system PROGRAM/ERASE)
   0.0V (MIN)/2.20V (MAX) F_VPP (in-system
    PROGRAM/ERASE)2
   12V ±5% (HV) F_V_PP (production programming
    compatibility)
• Asynchronous access time1
   Flash access time: 100ns or 110ns @ 1.65V F_V_CC
   SRAM access time: 100ns @ 1.65V S_V_CC
• Page Mode read access1
   Interpage read access: 100ns/110ns @ 1.65V F_V_CC
   Intrapage read access: 35ns/45ns @ 1.65V F_V_CC
• Low power consumption
• Enhanced suspend options
   ERASE-SUSPEND-to-READ within same bank
   PROGRAM-SUSPEND-to-READ within same bank
   ERASE-SUSPEND-to-PROGRAM within same bank
• Read/Write SRAM during program/erase of Flash
• Dual 64-bit chip protection registers for security
   purposes
• PROGRAM/ERASE cycles
   100,000 WRITE/ERASE cycles per block
• Cross-compatible command set support
   Extended command set
   Common Flash interface (CFI) compliant

The MT28C3212P2FL and MT28C3212P2NFL combination Flash and SRAM memory devices provide a compact, low-power solution for systems where PCB real estate is at a premium. The dual-bank Flash is a high performance, high-density, nonvolatile memory device with a revolutionary architecture that can significantly improve system performance.

This new architecture of MT28C3212P2NFL features:

• A two-memory-bank configuration supporting
   dual-bank burst operation;

• A high-performance bus interface providing a fast
   page data transfer; and

• A conventional asynchronous bus interface.

The MT28C3212P2NFL also provides soft protection for blocks by configuring soft protection registers with dedicated command sequences. For security purposes, dual 64- bit chip protection registers are provided.

The embedded WORD WRITE and BLOCK ERASE functions of MT28C3212P2NFL are fully automated by an on-chip write state machine (WSM). The WSM simplifies these operations and relieves the system processor of secondary tasks. An on-chip status register of MT28C3212P2NFL, one for each bank, can be used to monitor the WSM status to determine the progress of a PROGRAM/ERASE command.

The erase/program suspend functionality of MT28C3212P2NFL allows compatibility with existing EEPROM emulation software packages.

The MT28C3212P2NFL takes advantage of a dedicated power source for the Flash device (F_V_CC) and a dedicated power source for the SRAM device (S_V_CC), both at 1.65V1.95V or 1.80V2.20V for optimized power consumption and improved noise immunity. The MT28C3212P2FL and MT28C3212P2NFL devices support two V_PP voltage ranges, V_PP1 and V_PP2. V_PP1 is an incircuit voltage of 0.9V2.2V (MT28C3212P2FL) or 0.0V 2.2V (MT28C3212P2NFL). V_PP2 is the production compatibility voltage of 12V ±5%. The 12V ±5% V_PP2 is supported for a maximum of 100 cycles and 10 cumulative hours. See Table 1.

The MT28C3212P2FL and MT28C3212P2NFL devices contain an asynchronous 2Mb SRAM organized as 128K-words by 16 bits. These devices are fabricated using an advanced CMOS process and high-speed/ ultra-low-power circuit technology.

The MT28C3212P2FL and MT28C3212P2NFL devices are packaged in a 66-ball FBGA package with 0.80mm pitch.