MSP50C614

The MSP50C614 is a low-cost, mixed-signal processor that combines a speech synthesizer, general-purpose I/O, onboard ROM, and direct speaker-drive in a single package. The computational unit utilizes a powerful new DSP which gives the MSP50C614 unprecedented speed and computational flexibility compared with previous devices of its type. The MSP50C614 supports a variety of speech and audio coding algorithms, providing a range of options with respect to speech duration and sound quality.

The MSP50C614 consists of a micro-DSP core, embedded program, and data memory, and a self-contained clock generation system. General-purpose periphery is comprised of 64 bits of partially configurable I/O. The core processor of MSP50C614 is a general-purpose 16-bit microcontroller with DSP capability. The basic core block includes computational unit (CU), data address unit, program address unit, two timers, eight level interrupt processor, and several system and control registers. The core processor gives the MSP50C614 break-point capability in emulation.

The processor MSP50C614 is Harvard type for efficient DSP algorithm execution. It requires separate program and data memory blocks to permit simultaneous access. It is configured in 32K 17-bit words.

The total ROM space of MSP50C614 is divided into two areas: 1) The lower 2K words are reserved by Texas Instruments for the purposes of a built-in self-test 2) The upper 30K is for user program/data.

The data memory is internal static RAM. The RAM is configured in 640 17-bit words. Both memories are designed to consume minimum power at a given system clock and algorithm acquisition frequency.

A flexible clock generation system of MSP50C614 enables the software to control the clock over a wide frequency range. The implementation uses a phase-locked loop (PLL) circuit that drives the processor clock at a selectable frequency between the minimum and maximum achievable. Selectable frequencies for the processor clock are spaced apart in 65.536 kHz steps. The PLL clock-reference of MSP50C614 is also selectable; either a resistor-trimmed oscillator or a crystal-referenced oscillator may be used. Internal and external clock sources are controlled separately to provide different levels of power management.

The periphery of MSP50C614 consists of five 8-bit wide general-purpose I/O ports, one 8-bit wide dedicated input port, and one 16-bit wide dedicated output port. The bidirectional I/O can be configured under software control as either high-impedance inputs or as totem-pole outputs. They are controlled via addressable I/O registers. The input-only port has a programmable pullup option (70-kΩ minimum resistance) and a dedicated service interrupt. These features of MSP50C614 make the input port especially useful as a key-scan interface.

A simple one-bit comparator  of MSP50C614 is also included in the periphery. The comparator is enabled by a control register, and its pin access is shared with two pins in one of the general-purpose I/O ports. Rounding out the MSP50C614 periphery is a built-in pulse-density-modulated DAC (digital-to-analog converter) with direct speaker-drive capability. The functional block diagram gives an overview of the MSP50C614 functionality.